jens 652dfe00a2 [Uart_wb] ...

- fixed: f_sysclk is in MHz

git-svn-id: http://moon:8086/svn/vhdl/trunk@1365 cc03376c-175c-47c8-b038-4cd826a8556b

2017-01-11 08:08:40 +00:00

Common

- added

2015-10-24 16:12:48 +00:00

lib

[Uart_wb]

2017-01-11 08:08:40 +00:00

projects

[DE0-Nano]

2017-01-07 15:34:40 +00:00

S

Description

No description provided

23 MiB

Languages

VHDL 90.1%

Verilog 4.2%

Tcl 2.5%

SystemVerilog 0.8%

IGOR Pro 0.5%

Other 1.5%