diff --git a/lib/uart/uart_wb.vhd b/lib/uart/uart_wb.vhd
index ad6eff1..4ae1d19 100644
--- a/lib/uart/uart_wb.vhd
+++ b/lib/uart/uart_wb.vhd
@@ -8,7 +8,7 @@ USE WORK.uart_types.all;
 ENTITY uart_wb IS
 	Generic 
 	(
-		f_sysclk			: real := 100.0e6;
+		f_sysclk			: real := 100.0;
 		baudrate_default	: real := 115200.0;
 		fifo_depth_bits		: integer := 4
 	);
@@ -100,7 +100,7 @@ registers_write:
 		if rising_edge(CLK_I) then
 			reg_we_uart_tx	<= '0';
 			if RST_I = '1' then
-				reg_uart_baud	<= to_unsigned(integer(0.5+f_sysclk/(16.0*baudrate_default))-1, 16);
+				reg_uart_baud	<= to_unsigned(integer(0.5+f_sysclk*1.0e6/(16.0*baudrate_default))-1, 16);
 				rx_int_en		<= '0';
 				tx_int_en		<= '0';
 			elsif (STB_I and CYC_I and WE_I) = '1' then