diff --git a/projects/mips_sys/src/tb_mips_sys.vhd b/projects/mips_sys/src/tb_mips_sys.vhd
index bbc9e1c..bf5589f 100644
--- a/projects/mips_sys/src/tb_mips_sys.vhd
+++ b/projects/mips_sys/src/tb_mips_sys.vhd
@@ -40,7 +40,8 @@ ARCHITECTURE behavior OF tb_mips_sys IS
 
 	constant CLK_PERIOD			: time := 10 ns;
 	constant AC97_CLK_PERIOD	: time := 83 ns;
-	constant ETH_CLK_PERIOD		: time := 40.7 ns;
+	constant ETH_CLK_PERIOD		: time := 7.7 ns;
+	constant LOOP_BACK_EN		: std_logic := '1';
 	signal sys_rst_n_in : std_logic := '0';
 	signal sys_clk_in : std_logic := '1';
 	signal dip  : unsigned(7 downto 0) := (others => '0');
@@ -237,6 +238,12 @@ uut: entity work.mips_sys
 		sys_error 				=> sys_error
 	);
 
+	sys_phy_rx		<= sys_phy_tx when LOOP_BACK_EN = '1' else X"00";
+	sys_phy_rx_dv	<= sys_phy_tx_en when LOOP_BACK_EN = '1' else '0';
+	sys_phy_rx_er	<= sys_phy_tx_er when LOOP_BACK_EN = '1' else '0';
+	sys_phy_crs		<= '0';
+	sys_phy_col		<= '0';
+
 inst_ssram : entity work.cy7c1354
     PORT MAP 
     (