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- minor change

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git-svn-id: http://moon:8086/svn/vhdl/trunk@1262 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2015-05-30 09:07:50 +00:00
parent ec35a40898
commit 5e4798bbab
2 changed files with 4 additions and 4 deletions
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lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb32.vhd
+2 -2
View File
@@ -218,7 +218,7 @@ begin
addr_fifo_in <= ADDR_I(24 downto 2) & "0";
tag_fifo_in <= "000" & ADDR_I(25);
u_cmd_we <= (not cat_fifo_empty) and (not u_busy);
u_cmd_we <= (not cat_fifo_empty);
u_cmd <= cmd_fifo_out;
u_addr <= addr_fifo_out;
phy_in.wr_dm <= ((BUS_DM_WIDTH/2-1 downto 0 => '1') & write_fifo_dm_out) when phy_out.tag_wr(0) = '0' else (write_fifo_dm_out & (BUS_DM_WIDTH/2-1 downto 0 => '1'));
@@ -226,7 +226,7 @@ begin
phy_in.wr_data <= write_fifo_data_out & write_fifo_data_out;
write_fifo_re <= phy_out.wr_data_re and (not write_fifo_empty);
cat_fifo_re <= u_cmd_we;
cat_fifo_re <= u_cmd_we and (not u_busy);
read_fifo_re <= (not read_fifo_empty) and MRDY_I;
read_fifo_we <= phy_out.rd_data_we;
read_fifo_data_in <= phy_out.rd_data(BUS_DATA_WIDTH/2-1 downto 0) when phy_out.tag_rd(0) = '0' else phy_out.rd_data(BUS_DATA_WIDTH-1 downto BUS_DATA_WIDTH/2);
lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb64.vhd
+2 -2
View File
@@ -218,7 +218,7 @@ begin
addr_fifo_in <= ADDR_I(25 downto 3) & "0";
tag_fifo_in <= "000" & ADDR_I(2);
u_cmd_we <= (not cat_fifo_empty) and (not u_busy);
u_cmd_we <= (not cat_fifo_empty);
u_cmd <= cmd_fifo_out;
u_addr <= addr_fifo_out;
phy_in.wr_dm <= (write_fifo_dm_out(BUS_DATA_WIDTH+BUS_DM_WIDTH-5 downto BUS_DATA_WIDTH) & write_fifo_dm_out(BUS_DATA_WIDTH+BUS_DM_WIDTH-1 downto BUS_DATA_WIDTH+4)) when phy_out.tag_wr(0) = '1' else write_fifo_dm_out(BUS_DATA_WIDTH+BUS_DM_WIDTH-1 downto BUS_DATA_WIDTH);
@@ -226,7 +226,7 @@ begin
phy_in.wr_data <= (write_fifo_data_out(BUS_DATA_WIDTH/2-1 downto 0) & write_fifo_data_out(BUS_DATA_WIDTH-1 downto BUS_DATA_WIDTH/2)) when phy_out.tag_wr(0) = '1' else write_fifo_data_out(BUS_DATA_WIDTH-1 downto 0);
write_fifo_re <= phy_out.wr_data_re and (not write_fifo_empty);
cat_fifo_re <= u_cmd_we;
cat_fifo_re <= u_cmd_we and (not u_busy);
read_fifo_re <= (not read_fifo_empty) and MRDY_I;
read_fifo_we <= phy_out.rd_data_we;
read_fifo_data_in <= (phy_out.rd_data(BUS_DATA_WIDTH/2-1 downto 0) & phy_out.rd_data(BUS_DATA_WIDTH-1 downto BUS_DATA_WIDTH/2)) when phy_out.tag_rd(0) = '1' else phy_out.rd_data(BUS_DATA_WIDTH-1 downto 0);