diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb32.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb32.vhd
index 2069d0b..2b0ac39 100644
--- a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb32.vhd
+++ b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb32.vhd
@@ -218,7 +218,7 @@ begin
 	addr_fifo_in		<= ADDR_I(24 downto 2) & "0";
 	tag_fifo_in			<= "000" & ADDR_I(25);
 	
-	u_cmd_we			<= (not cat_fifo_empty) and (not u_busy);
+	u_cmd_we			<= (not cat_fifo_empty);
 	u_cmd				<= cmd_fifo_out;
 	u_addr				<= addr_fifo_out;
 	phy_in.wr_dm		<= ((BUS_DM_WIDTH/2-1 downto 0 => '1') & write_fifo_dm_out) when phy_out.tag_wr(0) = '0' else (write_fifo_dm_out & (BUS_DM_WIDTH/2-1 downto 0 => '1'));
@@ -226,7 +226,7 @@ begin
 	phy_in.wr_data		<= write_fifo_data_out & write_fifo_data_out;
 	
 	write_fifo_re		<= phy_out.wr_data_re and (not write_fifo_empty);
-	cat_fifo_re			<= u_cmd_we;
+	cat_fifo_re			<= u_cmd_we and (not u_busy);
 	read_fifo_re 		<= (not read_fifo_empty) and MRDY_I;
 	read_fifo_we		<= phy_out.rd_data_we;
 	read_fifo_data_in	<= phy_out.rd_data(BUS_DATA_WIDTH/2-1 downto 0) when phy_out.tag_rd(0) = '0' else phy_out.rd_data(BUS_DATA_WIDTH-1 downto BUS_DATA_WIDTH/2);	
diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb64.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb64.vhd
index e12b14d..f8488fe 100644
--- a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb64.vhd
+++ b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb64.vhd
@@ -218,7 +218,7 @@ begin
 	addr_fifo_in		<= ADDR_I(25 downto 3) & "0";
 	tag_fifo_in			<= "000" & ADDR_I(2);
 	
-	u_cmd_we			<= (not cat_fifo_empty) and (not u_busy);
+	u_cmd_we			<= (not cat_fifo_empty);
 	u_cmd				<= cmd_fifo_out;
 	u_addr				<= addr_fifo_out;
 	phy_in.wr_dm		<= (write_fifo_dm_out(BUS_DATA_WIDTH+BUS_DM_WIDTH-5 downto BUS_DATA_WIDTH) & write_fifo_dm_out(BUS_DATA_WIDTH+BUS_DM_WIDTH-1 downto BUS_DATA_WIDTH+4)) when phy_out.tag_wr(0) = '1' else write_fifo_dm_out(BUS_DATA_WIDTH+BUS_DM_WIDTH-1 downto BUS_DATA_WIDTH);
@@ -226,7 +226,7 @@ begin
 	phy_in.wr_data		<= (write_fifo_data_out(BUS_DATA_WIDTH/2-1 downto 0) & write_fifo_data_out(BUS_DATA_WIDTH-1 downto BUS_DATA_WIDTH/2)) when phy_out.tag_wr(0) = '1' else write_fifo_data_out(BUS_DATA_WIDTH-1 downto 0);
 	
 	write_fifo_re		<= phy_out.wr_data_re and (not write_fifo_empty);
-	cat_fifo_re			<= u_cmd_we;
+	cat_fifo_re			<= u_cmd_we and (not u_busy);
 	read_fifo_re 		<= (not read_fifo_empty) and MRDY_I;
 	read_fifo_we		<= phy_out.rd_data_we;
 	read_fifo_data_in	<= (phy_out.rd_data(BUS_DATA_WIDTH/2-1 downto 0) & phy_out.rd_data(BUS_DATA_WIDTH-1 downto BUS_DATA_WIDTH/2)) when phy_out.tag_rd(0) = '1' else phy_out.rd_data(BUS_DATA_WIDTH-1 downto 0);