- refactored
git-svn-id: http://moon:8086/svn/vhdl/trunk@1531 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
@@ -0,0 +1,30 @@
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[*]
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[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
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[*] Wed Mar 24 18:10:46 2021
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[*]
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[dumpfile] "/home/jens/work/vhdl/trunk/lib/JBUS/ghdl/build/tb_ram_wb/tb_ram_wb.vcd"
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[dumpfile_mtime] "Wed Mar 24 18:09:02 2021"
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[dumpfile_size] 39259
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[savefile] "/home/jens/work/vhdl/trunk/lib/JBUS/ghdl/build/tb_ram_wb/tb_ram_wb.gtkw"
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[timestart] 0
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[size] 1856 1136
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[pos] -51 -51
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*-27.715721 354000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
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[treeopen] tb_ram_wb.
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[treeopen] tb_ram_wb.inst_ram_wb.
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[sst_width] 233
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[signals_width] 212
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[sst_expanded] 1
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[sst_vpaned_height] 331
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@28
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tb_ram_wb.rst_o
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tb_ram_wb.clk_o
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tb_ram_wb.ack_i
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@29
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tb_ram_wb.we_o
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@22
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tb_ram_wb.addr_o[31:0]
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tb_ram_wb.dat_i[31:0]
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tb_ram_wb.dat_o[31:0]
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[pattern_trace] 1
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[pattern_trace] 0
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@@ -0,0 +1,18 @@
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ROOT_PATH := ../../..
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LIB_PATH := $(ROOT_PATH)/lib
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MOD_PATH := $(LIB_PATH)/JBUS
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SRCS += $(LIB_PATH)/misc/utils_pkg.vhd
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SRCS += $(LIB_PATH)/rams/sim/dpram_1w1r1c_ra.vhd
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SRCS += $(MOD_PATH)/src/memory/ram_wb.vhd
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SRCS += $(MOD_PATH)/src/memory/tb_ram_wb.vhd
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# Compile
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TARGET := tb_ram_wb
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ENTITY := tb_ram_wb
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WITH_VCD := y
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RUN_TIME := 1500ns
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include $(ROOT_PATH)/Common/make/ghdl.mk
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@@ -0,0 +1,30 @@
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[*]
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[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
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||||
[*] Wed Mar 24 18:18:00 2021
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[*]
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[dumpfile] "/home/jens/work/vhdl/trunk/lib/JBUS/ghdl/build/tb_rom_wb/tb_rom_wb.vcd"
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[dumpfile_mtime] "Wed Mar 24 18:17:07 2021"
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[dumpfile_size] 24044
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[savefile] "/home/jens/work/vhdl/trunk/lib/JBUS/ghdl/build/tb_rom_wb/tb_rom_wb.gtkw"
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[timestart] 0
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[size] 1856 1136
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[pos] -51 -51
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*-27.727428 114000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
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[sst_width] 233
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[signals_width] 223
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[sst_expanded] 1
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[sst_vpaned_height] 331
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@28
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tb_rom_wb.clk_o
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tb_rom_wb.rst_o
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@22
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tb_rom_wb.addr_o[31:0]
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tb_rom_wb.dat_i[31:0]
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@28
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tb_rom_wb.mrdy_o
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tb_rom_wb.srdy_i
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tb_rom_wb.stb_o
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@29
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tb_rom_wb.cyc_o
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[pattern_trace] 1
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[pattern_trace] 0
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@@ -0,0 +1,17 @@
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ROOT_PATH := ../../..
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LIB_PATH := $(ROOT_PATH)/lib
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MOD_PATH := $(LIB_PATH)/JBUS
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SRCS += $(MOD_PATH)/src/memory/rom_sim.vhd
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SRCS += $(MOD_PATH)/src/memory/rom_wb.vhd
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SRCS += $(MOD_PATH)/src/memory/tb_rom_wb.vhd
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# Compile
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TARGET := tb_rom_wb
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ENTITY := tb_rom_wb
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WITH_VCD := y
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RUN_TIME := 1500ns
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include $(ROOT_PATH)/Common/make/ghdl.mk
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@@ -0,0 +1,17 @@
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## NOTE: Do not edit this file.
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##
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vlib work
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# Top and TB
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vcom -explicit -93 "../utils_pkg.vhd"
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vcom -explicit -93 "../../rams/dpram_1w1r1c_ra_sim.vhd"
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vcom -explicit -93 "../ram_wb.vhd"
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vcom -explicit -93 "../tb_ram_wb.vhd"
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vsim -t 1ps -lib work tb_ram_wb
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do {tb_ram_wb.wdo}
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view wave
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view structure
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view signals
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run 1.5us
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@@ -0,0 +1,33 @@
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onerror {resume}
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quietly WaveActivateNextPane {} 0
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add wave -noupdate -format Logic /tb_ram_wb/clk_o
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add wave -noupdate -format Logic /tb_ram_wb/rst_o
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add wave -noupdate -format Logic /tb_ram_wb/cyc_o
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add wave -noupdate -format Logic /tb_ram_wb/stb_o
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add wave -noupdate -format Logic /tb_ram_wb/we_o
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add wave -noupdate -format Literal /tb_ram_wb/sel_o
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add wave -noupdate -format Logic /tb_ram_wb/ack_i
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add wave -noupdate -format Logic /tb_ram_wb/mrdy_o
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add wave -noupdate -format Logic /tb_ram_wb/srdy_i
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add wave -noupdate -format Literal -radix hexadecimal /tb_ram_wb/addr_o
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add wave -noupdate -format Literal -radix hexadecimal /tb_ram_wb/dat_i
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add wave -noupdate -format Literal -radix hexadecimal /tb_ram_wb/dat_o
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add wave -noupdate -format Literal -radix hexadecimal /tb_ram_wb/dout_reg
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add wave -noupdate -format Literal /tb_ram_wb/dout_cnt
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add wave -noupdate -format Literal -radix hexadecimal -expand /tb_ram_wb/inst_ram_wb/inst_ram/sram
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TreeUpdate [SetDefaultTree]
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WaveRestoreCursors {{Cursor 1} {23564 ps} 0}
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configure wave -namecolwidth 150
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configure wave -valuecolwidth 100
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configure wave -justifyvalue left
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configure wave -signalnamewidth 1
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configure wave -snapdistance 10
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configure wave -datasetprefix 0
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configure wave -rowmargin 4
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configure wave -childrowmargin 2
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configure wave -gridoffset 0
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configure wave -gridperiod 1
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configure wave -griddelta 40
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configure wave -timeline 0
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update
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WaveRestoreZoom {0 ps} {179430 ps}
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||||
@@ -0,0 +1,16 @@
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## NOTE: Do not edit this file.
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##
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vlib work
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# Top and TB
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vcom -explicit -93 "../rom_sim.vhd"
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vcom -explicit -93 "../rom_wb.vhd"
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vcom -explicit -93 "../tb_rom_wb.vhd"
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vsim -t 1ps -lib work tb_rom_wb
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do {tb_rom_wb.wdo}
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view wave
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view structure
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view signals
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run 1us
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@@ -0,0 +1,29 @@
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onerror {resume}
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quietly WaveActivateNextPane {} 0
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add wave -noupdate -format Logic /tb_rom_wb/clk_o
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add wave -noupdate -format Logic /tb_rom_wb/rst_o
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add wave -noupdate -format Logic /tb_rom_wb/cyc_o
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add wave -noupdate -format Logic /tb_rom_wb/stb_o
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add wave -noupdate -format Logic /tb_rom_wb/ack_i
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add wave -noupdate -format Logic /tb_rom_wb/mrdy_o
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add wave -noupdate -format Logic /tb_rom_wb/srdy_i
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add wave -noupdate -format Literal -radix hexadecimal /tb_rom_wb/addr_o
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add wave -noupdate -format Literal -radix hexadecimal /tb_rom_wb/dat_i
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add wave -noupdate -format Literal -radix hexadecimal /tb_rom_wb/dout_reg
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add wave -noupdate -format Literal /tb_rom_wb/dout_cnt
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TreeUpdate [SetDefaultTree]
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WaveRestoreCursors {{Cursor 1} {796036 ps} 0}
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configure wave -namecolwidth 150
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configure wave -valuecolwidth 100
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configure wave -justifyvalue left
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configure wave -signalnamewidth 1
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configure wave -snapdistance 10
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configure wave -datasetprefix 0
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configure wave -rowmargin 4
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configure wave -childrowmargin 2
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configure wave -gridoffset 0
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configure wave -gridperiod 1
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configure wave -griddelta 40
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configure wave -timeline 0
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update
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WaveRestoreZoom {0 ps} {1050 ns}
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@@ -0,0 +1,126 @@
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LIBRARY IEEE;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE IEEE.NUMERIC_STD.ALL;
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library work;
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use work.utils_pkg.all;
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ENTITY ram_wb IS
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GENERIC
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(
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NUM_WORDS : integer := 64
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);
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Port
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(
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CLK_I : in STD_LOGIC;
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RST_I : in STD_LOGIC;
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CYC_I : in STD_LOGIC;
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||||
STB_I : in STD_LOGIC;
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||||
SEL_I : in unsigned(3 downto 0);
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||||
WE_I : in STD_LOGIC;
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ACK_O : out STD_LOGIC;
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||||
SRDY_O : out STD_LOGIC;
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||||
MRDY_I : in STD_LOGIC;
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||||
ADDR_I : in unsigned(31 downto 0);
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||||
DAT_I : in unsigned(31 downto 0);
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||||
DAT_O : out unsigned(31 downto 0)
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||||
);
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END ram_wb;
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||||
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ARCHITECTURE behavior OF ram_wb IS
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constant addr_width : natural := NextExpBaseTwo(NUM_WORDS);
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signal ram_en : std_logic;
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signal we : unsigned(3 downto 0);
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||||
signal re : std_logic;
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||||
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begin
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||||
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||||
SRDY_O <= CYC_I;
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||||
|
||||
ram_en <= CYC_I and STB_I and MRDY_I;
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we <= SEL_I and (3 downto 0 => ram_en and WE_I);
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re <= ram_en and not WE_I;
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||||
|
||||
data_valid_register:
|
||||
process(CLK_I)
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||||
begin
|
||||
if rising_edge(CLK_I) then
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||||
if RST_I = '1' then
|
||||
ACK_O <= '0';
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||||
else
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ACK_O <= re;
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end if;
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||||
end if;
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||||
end process;
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||||
|
||||
inst_ram_0 : entity work.dpram_1w1r1c_ra
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GENERIC MAP
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||||
(
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||||
addr_width => addr_width,
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data_width => 8
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||||
)
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||||
PORT MAP
|
||||
(
|
||||
clk => CLK_I,
|
||||
we_a => we(0),
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re_b => '1',
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||||
addr_a => ADDR_I(addr_width+1 downto 2),
|
||||
addr_b => ADDR_I(addr_width+1 downto 2),
|
||||
din_a => DAT_I(7 downto 0),
|
||||
dout_b => DAT_O(7 downto 0)
|
||||
);
|
||||
|
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inst_ram_1 : entity work.dpram_1w1r1c_ra
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GENERIC MAP
|
||||
(
|
||||
addr_width => addr_width,
|
||||
data_width => 8
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
clk => CLK_I,
|
||||
we_a => we(1),
|
||||
re_b => '1',
|
||||
addr_a => ADDR_I(addr_width+1 downto 2),
|
||||
addr_b => ADDR_I(addr_width+1 downto 2),
|
||||
din_a => DAT_I(15 downto 8),
|
||||
dout_b => DAT_O(15 downto 8)
|
||||
);
|
||||
|
||||
inst_ram_2 : entity work.dpram_1w1r1c_ra
|
||||
GENERIC MAP
|
||||
(
|
||||
addr_width => addr_width,
|
||||
data_width => 8
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
clk => CLK_I,
|
||||
we_a => we(2),
|
||||
re_b => '1',
|
||||
addr_a => ADDR_I(addr_width+1 downto 2),
|
||||
addr_b => ADDR_I(addr_width+1 downto 2),
|
||||
din_a => DAT_I(23 downto 16),
|
||||
dout_b => DAT_O(23 downto 16)
|
||||
);
|
||||
|
||||
inst_ram_3 : entity work.dpram_1w1r1c_ra
|
||||
GENERIC MAP
|
||||
(
|
||||
addr_width => addr_width,
|
||||
data_width => 8
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
clk => CLK_I,
|
||||
we_a => we(3),
|
||||
re_b => '1',
|
||||
addr_a => ADDR_I(addr_width+1 downto 2),
|
||||
addr_b => ADDR_I(addr_width+1 downto 2),
|
||||
din_a => DAT_I(31 downto 24),
|
||||
dout_b => DAT_O(31 downto 24)
|
||||
);
|
||||
|
||||
|
||||
end behavior;
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,62 @@
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
ENTITY rom_wb IS
|
||||
Port
|
||||
(
|
||||
CLK_I : in STD_LOGIC;
|
||||
RST_I : in STD_LOGIC;
|
||||
CYC_I : in STD_LOGIC;
|
||||
WE_I : in STD_LOGIC;
|
||||
STB_I : in STD_LOGIC;
|
||||
ACK_O : out STD_LOGIC;
|
||||
MRDY_I : in STD_LOGIC;
|
||||
SRDY_O : out STD_LOGIC;
|
||||
ADDR_I : in unsigned(31 downto 0);
|
||||
DAT_O : out unsigned(31 downto 0)
|
||||
);
|
||||
END rom_wb;
|
||||
|
||||
ARCHITECTURE behavior OF rom_wb IS
|
||||
|
||||
COMPONENT rom
|
||||
PORT
|
||||
(
|
||||
clk : in STD_LOGIC;
|
||||
ce : in STD_LOGIC;
|
||||
addr : in unsigned(31 downto 0);
|
||||
dout : out unsigned(31 downto 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
signal data_en : std_logic;
|
||||
|
||||
begin
|
||||
|
||||
data_en <= CYC_I and STB_I and MRDY_I;
|
||||
SRDY_O <= CYC_I;
|
||||
|
||||
data_valid_register:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
if RST_I = '1' then
|
||||
ACK_O <= '0';
|
||||
else
|
||||
ACK_O <= data_en and not WE_I;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
inst_rom : rom
|
||||
PORT MAP
|
||||
(
|
||||
clk => CLK_I,
|
||||
ce => data_en,
|
||||
addr => ADDR_I,
|
||||
dout => DAT_O
|
||||
);
|
||||
|
||||
|
||||
end behavior;
|
||||
@@ -0,0 +1,414 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: testbench for system test using Xilinx ML-402
|
||||
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
|
||||
-- This library is free software; you can redistribute it and/or
|
||||
-- modify it under the terms of the GNU Lesser General Public
|
||||
-- License as published by the Free Software Foundation; either
|
||||
-- version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
-- This library is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
-- Lesser General Public License for more details.
|
||||
|
||||
-- You should have received a copy of the GNU Lesser General Public
|
||||
-- License along with this library; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
use std.textio.all; -- Imports the standard textio package.
|
||||
|
||||
ENTITY tb_ram_wb IS
|
||||
END tb_ram_wb;
|
||||
|
||||
ARCHITECTURE behavior OF tb_ram_wb IS
|
||||
|
||||
constant CLK_PERIOD : time := 10 ns;
|
||||
constant RAM_NUM_WORDS : integer := 256;
|
||||
|
||||
signal CLK_O : std_logic := '1';
|
||||
signal RST_O : std_logic := '1';
|
||||
signal CYC_O : std_logic := '0';
|
||||
signal STB_O : std_logic := '0';
|
||||
signal WE_O : std_logic := '0';
|
||||
signal SEL_O : unsigned(3 downto 0) := (others => '1');
|
||||
signal ACK_I : std_logic;
|
||||
signal MRDY_O : std_logic := '1';
|
||||
signal SRDY_I : std_logic;
|
||||
signal ADDR_O : unsigned(31 downto 0) := (others => '-');
|
||||
signal DAT_I : unsigned(31 downto 0);
|
||||
signal DAT_O : unsigned(31 downto 0) := (others => '-');
|
||||
|
||||
signal dout_rst : std_logic := '0';
|
||||
signal dout_reg : unsigned(31 downto 0);
|
||||
signal dout_cnt : natural range 0 to 255;
|
||||
|
||||
BEGIN
|
||||
|
||||
inst_ram_wb : entity work.ram_wb
|
||||
GENERIC MAP
|
||||
(
|
||||
NUM_WORDS => RAM_NUM_WORDS
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
RST_I => RST_O,
|
||||
CLK_I => CLK_O,
|
||||
CYC_I => CYC_O,
|
||||
STB_I => STB_O,
|
||||
SEL_I => SEL_O,
|
||||
WE_I => WE_O,
|
||||
ACK_O => ACK_I,
|
||||
SRDY_O => SRDY_I,
|
||||
MRDY_I => MRDY_O,
|
||||
ADDR_I => ADDR_O,
|
||||
DAT_I => DAT_O,
|
||||
DAT_O => DAT_I
|
||||
);
|
||||
|
||||
read_register:
|
||||
process(CLK_O)
|
||||
begin
|
||||
if rising_edge(CLK_O) then
|
||||
if dout_rst = '1' then
|
||||
dout_cnt <= 0;
|
||||
elsif ACK_I = '1' and WE_O = '0' then
|
||||
dout_reg <= DAT_I;
|
||||
dout_cnt <= dout_cnt + 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
CLK_GEN: process
|
||||
begin
|
||||
wait for CLK_PERIOD/2;
|
||||
CLK_O <= not CLK_O;
|
||||
end process;
|
||||
|
||||
STIMULUS: process
|
||||
|
||||
begin
|
||||
|
||||
wait for 3*CLK_PERIOD;
|
||||
RST_O <= '0';
|
||||
|
||||
-- 8 single cycles
|
||||
CYC_O <= '1';
|
||||
STB_O <= '1';
|
||||
WE_O <= '1';
|
||||
DAT_O <= X"1234_CAF0";
|
||||
ADDR_O <= X"0000_0000";
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
DAT_O <= DAT_O + 1;
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
DAT_O <= DAT_O + 1;
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
DAT_O <= DAT_O + 1;
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
DAT_O <= DAT_O + 1;
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
DAT_O <= DAT_O + 1;
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
DAT_O <= DAT_O + 1;
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
DAT_O <= DAT_O + 1;
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
DAT_O <= DAT_O + 1;
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
DAT_O <= DAT_O + 1;
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
DAT_O <= DAT_O + 1;
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
DAT_O <= DAT_O + 1;
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
DAT_O <= DAT_O + 1;
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
DAT_O <= DAT_O + 1;
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
DAT_O <= DAT_O + 1;
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
DAT_O <= DAT_O + 1;
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
DAT_O <= DAT_O + 1;
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
DAT_O <= DAT_O + 1;
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
DAT_O <= DAT_O + 1;
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
DAT_O <= DAT_O + 1;
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
DAT_O <= DAT_O + 1;
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
DAT_O <= DAT_O + 1;
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
DAT_O <= DAT_O + 1;
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
DAT_O <= DAT_O + 1;
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
DAT_O <= DAT_O + 1;
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
DAT_O <= DAT_O + 1;
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
DAT_O <= DAT_O + 1;
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
DAT_O <= DAT_O + 1;
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
DAT_O <= DAT_O + 1;
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
DAT_O <= DAT_O + 1;
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
DAT_O <= DAT_O + 1;
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
DAT_O <= DAT_O + 1;
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
DAT_O <= DAT_O + 1;
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
DAT_O <= DAT_O + 1;
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
DAT_O <= DAT_O + 1;
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
DAT_O <= DAT_O + 1;
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
DAT_O <= DAT_O + 1;
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
DAT_O <= DAT_O + 1;
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
STB_O <= '0';
|
||||
wait until rising_edge(CLK_O);
|
||||
CYC_O <= '0';
|
||||
|
||||
|
||||
-- 8-word burst cycle
|
||||
wait for 3*CLK_PERIOD;
|
||||
dout_rst <= '1';
|
||||
wait until rising_edge(CLK_O);
|
||||
dout_rst <= '0';
|
||||
CYC_O <= '1';
|
||||
STB_O <= '1';
|
||||
WE_O <= '0';
|
||||
ADDR_O <= X"0000_0000";
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
STB_O <= '0';
|
||||
|
||||
wait until rising_edge(CLK_O) and dout_cnt = 7;
|
||||
CYC_O <= '0';
|
||||
|
||||
wait for 3*CLK_PERIOD;
|
||||
wait until rising_edge(CLK_O);
|
||||
-- 1-word burst cycle
|
||||
CYC_O <= '1';
|
||||
STB_O <= '1';
|
||||
WE_O <= '1';
|
||||
SEL_O <= "0011";
|
||||
ADDR_O <= X"0000_0080";
|
||||
DAT_O <= X"DEADBEEF";
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
STB_O <= '0';
|
||||
wait until rising_edge(CLK_O);
|
||||
CYC_O <= '0';
|
||||
|
||||
wait for 3*CLK_PERIOD;
|
||||
wait until rising_edge(CLK_O);
|
||||
-- 1-word burst cycle
|
||||
CYC_O <= '1';
|
||||
STB_O <= '1';
|
||||
WE_O <= '0';
|
||||
ADDR_O <= X"0000_0080";
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
STB_O <= '0';
|
||||
wait until rising_edge(CLK_O);
|
||||
CYC_O <= '0';
|
||||
|
||||
-- 8-word burst cycle
|
||||
wait for 3*CLK_PERIOD;
|
||||
dout_rst <= '1';
|
||||
wait until rising_edge(CLK_O);
|
||||
dout_rst <= '0';
|
||||
CYC_O <= '1';
|
||||
STB_O <= '1';
|
||||
WE_O <= '0';
|
||||
ADDR_O <= X"0000_0000";
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
STB_O <= '0';
|
||||
MRDY_O <= '0';
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
STB_O <= '1';
|
||||
MRDY_O <= '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
STB_O <= '0';
|
||||
|
||||
wait until rising_edge(CLK_O) and dout_cnt = 54;
|
||||
CYC_O <= '0';
|
||||
|
||||
wait;
|
||||
|
||||
end process;
|
||||
|
||||
END;
|
||||
@@ -0,0 +1,224 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: testbench for system test using Xilinx ML-402
|
||||
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
|
||||
-- This library is free software; you can redistribute it and/or
|
||||
-- modify it under the terms of the GNU Lesser General Public
|
||||
-- License as published by the Free Software Foundation; either
|
||||
-- version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
-- This library is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
-- Lesser General Public License for more details.
|
||||
|
||||
-- You should have received a copy of the GNU Lesser General Public
|
||||
-- License along with this library; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
use std.textio.all; -- Imports the standard textio package.
|
||||
|
||||
ENTITY tb_rom_wb IS
|
||||
END tb_rom_wb;
|
||||
|
||||
ARCHITECTURE behavior OF tb_rom_wb IS
|
||||
|
||||
constant CLK_PERIOD : time := 10 ns;
|
||||
signal CLK_O : std_logic := '1';
|
||||
signal RST_O : std_logic := '1';
|
||||
signal CYC_O : std_logic := '0';
|
||||
signal STB_O : std_logic := '0';
|
||||
signal ACK_I : std_logic;
|
||||
signal MRDY_O : std_logic := '1';
|
||||
signal SRDY_I : std_logic;
|
||||
signal ADDR_O : unsigned(31 downto 0) := (others => '-');
|
||||
signal DAT_I : unsigned(31 downto 0);
|
||||
|
||||
signal dout_rst : std_logic := '0';
|
||||
signal dout_reg : unsigned(31 downto 0);
|
||||
signal dout_cnt : natural range 0 to 255;
|
||||
|
||||
BEGIN
|
||||
|
||||
inst_rom_wb : entity work.rom_wb
|
||||
PORT MAP
|
||||
(
|
||||
RST_I => RST_O,
|
||||
CLK_I => CLK_O,
|
||||
CYC_I => CYC_O,
|
||||
STB_I => STB_O,
|
||||
WE_I => '0',
|
||||
ACK_O => ACK_I,
|
||||
SRDY_O => SRDY_I,
|
||||
MRDY_I => MRDY_O,
|
||||
ADDR_I => ADDR_O,
|
||||
DAT_O => DAT_I
|
||||
);
|
||||
|
||||
read_register:
|
||||
process(CLK_O)
|
||||
begin
|
||||
if rising_edge(CLK_O) then
|
||||
if dout_rst = '1' then
|
||||
dout_cnt <= 0;
|
||||
elsif ACK_I = '1' then
|
||||
dout_reg <= DAT_I;
|
||||
dout_cnt <= dout_cnt + 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
CLK_GEN: process
|
||||
begin
|
||||
wait for CLK_PERIOD/2;
|
||||
CLK_O <= not CLK_O;
|
||||
end process;
|
||||
|
||||
STIMULUS: process
|
||||
|
||||
begin
|
||||
|
||||
wait for 3*CLK_PERIOD;
|
||||
RST_O <= '0';
|
||||
|
||||
-- 8-word burst cycle
|
||||
wait for 3*CLK_PERIOD;
|
||||
dout_rst <= '1';
|
||||
wait until rising_edge(CLK_O);
|
||||
dout_rst <= '0';
|
||||
CYC_O <= '1';
|
||||
STB_O <= '1';
|
||||
ADDR_O <= X"0000_0180";
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
STB_O <= '0';
|
||||
MRDY_O <= '0';
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
STB_O <= '1';
|
||||
MRDY_O <= '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
ADDR_O <= ADDR_O + 4;
|
||||
wait until rising_edge(CLK_O) and SRDY_I = '1';
|
||||
STB_O <= '0';
|
||||
|
||||
wait until rising_edge(CLK_O) and dout_cnt = 54;
|
||||
CYC_O <= '0';
|
||||
|
||||
wait;
|
||||
|
||||
end process;
|
||||
|
||||
END;
|
||||
Reference in New Issue
Block a user