From 599726a7b2ee363da2f8e9258b94db548d1a7a87 Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Wed, 24 Mar 2021 18:39:05 +0000 Subject: [PATCH] - refactored git-svn-id: http://moon:8086/svn/vhdl/trunk@1531 cc03376c-175c-47c8-b038-4cd826a8556b --- lib/JBUS/{src/async_port => async_port/src}/async_port_wb.vhd | 0 lib/JBUS/{src/async_port => async_port/src}/async_types.vhd | 0 lib/JBUS/{ => busmaster}/ghdl/tb_busmaster_async.gtkw | 0 lib/JBUS/{ => busmaster}/ghdl/tb_busmaster_async.make | 0 lib/JBUS/{ => busmaster}/ghdl/tb_busmaster_sync.gtkw | 0 lib/JBUS/{ => busmaster}/ghdl/tb_busmaster_sync.make | 0 lib/JBUS/{ => busmaster}/sim/tb_busmaster_async.fdo | 0 lib/JBUS/{ => busmaster}/sim/tb_busmaster_async.wdo | 0 lib/JBUS/{ => busmaster}/sim/tb_busmaster_sync.fdo | 0 lib/JBUS/{ => busmaster}/sim/tb_busmaster_sync.wdo | 0 lib/JBUS/{src/busmaster => busmaster/src}/busmaster_async.vhd | 0 lib/JBUS/{src/busmaster => busmaster/src}/busmaster_async_new.vhd | 0 lib/JBUS/{src/busmaster => busmaster/src}/busmaster_sync.vhd | 0 lib/JBUS/{src/busmaster => busmaster/src}/busmaster_types.vhd | 0 lib/JBUS/{src/busmaster => busmaster/src}/tb_busmaster_async.vhd | 0 lib/JBUS/{src/busmaster => busmaster/src}/tb_busmaster_sync.vhd | 0 lib/JBUS/{ => dmac}/ghdl/tb_dmac_sync.gtkw | 0 lib/JBUS/{ => dmac}/ghdl/tb_dmac_sync.make | 0 lib/JBUS/{ => dmac}/sim/tb_dmac.fdo | 0 lib/JBUS/{ => dmac}/sim/tb_dmac.wdo | 0 lib/JBUS/{src/dmac => dmac/src}/dmac.vhd | 0 lib/JBUS/{src/dmac => dmac/src}/tb_dmac.vhd | 0 lib/JBUS/{src/flash_port => flash_port/src}/flash_port_wb.vhd | 0 lib/JBUS/{src/gpio => gpio/src}/gpio_wb.vhd | 0 lib/JBUS/{ => memory}/ghdl/tb_ram_wb.gtkw | 0 lib/JBUS/{ => memory}/ghdl/tb_ram_wb.make | 0 lib/JBUS/{ => memory}/ghdl/tb_rom_wb.gtkw | 0 lib/JBUS/{ => memory}/ghdl/tb_rom_wb.make | 0 lib/JBUS/{ => memory}/sim/tb_ram_wb.fdo | 0 lib/JBUS/{ => memory}/sim/tb_ram_wb.wdo | 0 lib/JBUS/{ => memory}/sim/tb_rom_wb.fdo | 0 lib/JBUS/{ => memory}/sim/tb_rom_wb.wdo | 0 lib/JBUS/{src/memory => memory/src}/ram_wb.vhd | 0 lib/JBUS/{src/memory => memory/src}/rom_sim.vhd | 0 lib/JBUS/{src/memory => memory/src}/rom_wb.vhd | 0 lib/JBUS/{src/memory => memory/src}/tb_ram_wb.vhd | 0 lib/JBUS/{src/memory => memory/src}/tb_rom_wb.vhd | 0 37 files changed, 0 insertions(+), 0 deletions(-) rename lib/JBUS/{src/async_port => async_port/src}/async_port_wb.vhd (100%) rename lib/JBUS/{src/async_port => async_port/src}/async_types.vhd (100%) rename lib/JBUS/{ => busmaster}/ghdl/tb_busmaster_async.gtkw (100%) rename lib/JBUS/{ => busmaster}/ghdl/tb_busmaster_async.make (100%) rename lib/JBUS/{ => busmaster}/ghdl/tb_busmaster_sync.gtkw (100%) rename lib/JBUS/{ => busmaster}/ghdl/tb_busmaster_sync.make (100%) rename lib/JBUS/{ => busmaster}/sim/tb_busmaster_async.fdo (100%) rename lib/JBUS/{ => busmaster}/sim/tb_busmaster_async.wdo (100%) rename lib/JBUS/{ => busmaster}/sim/tb_busmaster_sync.fdo (100%) rename lib/JBUS/{ => busmaster}/sim/tb_busmaster_sync.wdo (100%) rename lib/JBUS/{src/busmaster => busmaster/src}/busmaster_async.vhd (100%) rename lib/JBUS/{src/busmaster => busmaster/src}/busmaster_async_new.vhd (100%) rename lib/JBUS/{src/busmaster => busmaster/src}/busmaster_sync.vhd (100%) rename lib/JBUS/{src/busmaster => busmaster/src}/busmaster_types.vhd (100%) rename lib/JBUS/{src/busmaster => busmaster/src}/tb_busmaster_async.vhd (100%) rename lib/JBUS/{src/busmaster => busmaster/src}/tb_busmaster_sync.vhd (100%) rename lib/JBUS/{ => dmac}/ghdl/tb_dmac_sync.gtkw (100%) rename lib/JBUS/{ => dmac}/ghdl/tb_dmac_sync.make (100%) rename lib/JBUS/{ => dmac}/sim/tb_dmac.fdo (100%) rename lib/JBUS/{ => dmac}/sim/tb_dmac.wdo (100%) rename lib/JBUS/{src/dmac => dmac/src}/dmac.vhd (100%) rename lib/JBUS/{src/dmac => dmac/src}/tb_dmac.vhd (100%) rename lib/JBUS/{src/flash_port => flash_port/src}/flash_port_wb.vhd (100%) rename lib/JBUS/{src/gpio => gpio/src}/gpio_wb.vhd (100%) rename lib/JBUS/{ => memory}/ghdl/tb_ram_wb.gtkw (100%) rename lib/JBUS/{ => memory}/ghdl/tb_ram_wb.make (100%) rename lib/JBUS/{ => memory}/ghdl/tb_rom_wb.gtkw (100%) rename lib/JBUS/{ => memory}/ghdl/tb_rom_wb.make (100%) rename lib/JBUS/{ => memory}/sim/tb_ram_wb.fdo (100%) rename lib/JBUS/{ => memory}/sim/tb_ram_wb.wdo (100%) rename lib/JBUS/{ => memory}/sim/tb_rom_wb.fdo (100%) rename lib/JBUS/{ => memory}/sim/tb_rom_wb.wdo (100%) rename lib/JBUS/{src/memory => memory/src}/ram_wb.vhd (100%) rename lib/JBUS/{src/memory => memory/src}/rom_sim.vhd (100%) rename lib/JBUS/{src/memory => memory/src}/rom_wb.vhd (100%) rename lib/JBUS/{src/memory => memory/src}/tb_ram_wb.vhd (100%) rename lib/JBUS/{src/memory => memory/src}/tb_rom_wb.vhd (100%) diff --git a/lib/JBUS/src/async_port/async_port_wb.vhd b/lib/JBUS/async_port/src/async_port_wb.vhd similarity index 100% rename from lib/JBUS/src/async_port/async_port_wb.vhd rename to lib/JBUS/async_port/src/async_port_wb.vhd diff --git a/lib/JBUS/src/async_port/async_types.vhd b/lib/JBUS/async_port/src/async_types.vhd similarity index 100% rename from lib/JBUS/src/async_port/async_types.vhd rename to lib/JBUS/async_port/src/async_types.vhd diff --git a/lib/JBUS/ghdl/tb_busmaster_async.gtkw b/lib/JBUS/busmaster/ghdl/tb_busmaster_async.gtkw similarity index 100% rename from lib/JBUS/ghdl/tb_busmaster_async.gtkw rename to lib/JBUS/busmaster/ghdl/tb_busmaster_async.gtkw diff --git a/lib/JBUS/ghdl/tb_busmaster_async.make b/lib/JBUS/busmaster/ghdl/tb_busmaster_async.make similarity index 100% rename from lib/JBUS/ghdl/tb_busmaster_async.make rename to lib/JBUS/busmaster/ghdl/tb_busmaster_async.make diff --git a/lib/JBUS/ghdl/tb_busmaster_sync.gtkw b/lib/JBUS/busmaster/ghdl/tb_busmaster_sync.gtkw similarity index 100% rename from lib/JBUS/ghdl/tb_busmaster_sync.gtkw rename to lib/JBUS/busmaster/ghdl/tb_busmaster_sync.gtkw diff --git a/lib/JBUS/ghdl/tb_busmaster_sync.make b/lib/JBUS/busmaster/ghdl/tb_busmaster_sync.make similarity index 100% rename from lib/JBUS/ghdl/tb_busmaster_sync.make rename to lib/JBUS/busmaster/ghdl/tb_busmaster_sync.make diff --git a/lib/JBUS/sim/tb_busmaster_async.fdo b/lib/JBUS/busmaster/sim/tb_busmaster_async.fdo similarity index 100% rename from lib/JBUS/sim/tb_busmaster_async.fdo rename to lib/JBUS/busmaster/sim/tb_busmaster_async.fdo diff --git a/lib/JBUS/sim/tb_busmaster_async.wdo b/lib/JBUS/busmaster/sim/tb_busmaster_async.wdo similarity index 100% rename from lib/JBUS/sim/tb_busmaster_async.wdo rename to lib/JBUS/busmaster/sim/tb_busmaster_async.wdo diff --git a/lib/JBUS/sim/tb_busmaster_sync.fdo b/lib/JBUS/busmaster/sim/tb_busmaster_sync.fdo similarity index 100% rename from lib/JBUS/sim/tb_busmaster_sync.fdo rename to lib/JBUS/busmaster/sim/tb_busmaster_sync.fdo diff --git a/lib/JBUS/sim/tb_busmaster_sync.wdo b/lib/JBUS/busmaster/sim/tb_busmaster_sync.wdo similarity index 100% rename from lib/JBUS/sim/tb_busmaster_sync.wdo rename to lib/JBUS/busmaster/sim/tb_busmaster_sync.wdo diff --git a/lib/JBUS/src/busmaster/busmaster_async.vhd b/lib/JBUS/busmaster/src/busmaster_async.vhd similarity index 100% rename from lib/JBUS/src/busmaster/busmaster_async.vhd rename to lib/JBUS/busmaster/src/busmaster_async.vhd diff --git a/lib/JBUS/src/busmaster/busmaster_async_new.vhd b/lib/JBUS/busmaster/src/busmaster_async_new.vhd similarity index 100% rename from lib/JBUS/src/busmaster/busmaster_async_new.vhd rename to lib/JBUS/busmaster/src/busmaster_async_new.vhd diff --git a/lib/JBUS/src/busmaster/busmaster_sync.vhd b/lib/JBUS/busmaster/src/busmaster_sync.vhd similarity index 100% rename from lib/JBUS/src/busmaster/busmaster_sync.vhd rename to lib/JBUS/busmaster/src/busmaster_sync.vhd diff --git a/lib/JBUS/src/busmaster/busmaster_types.vhd b/lib/JBUS/busmaster/src/busmaster_types.vhd similarity index 100% rename from lib/JBUS/src/busmaster/busmaster_types.vhd rename to lib/JBUS/busmaster/src/busmaster_types.vhd diff --git a/lib/JBUS/src/busmaster/tb_busmaster_async.vhd b/lib/JBUS/busmaster/src/tb_busmaster_async.vhd similarity index 100% rename from lib/JBUS/src/busmaster/tb_busmaster_async.vhd rename to lib/JBUS/busmaster/src/tb_busmaster_async.vhd diff --git a/lib/JBUS/src/busmaster/tb_busmaster_sync.vhd b/lib/JBUS/busmaster/src/tb_busmaster_sync.vhd similarity index 100% rename from lib/JBUS/src/busmaster/tb_busmaster_sync.vhd rename to lib/JBUS/busmaster/src/tb_busmaster_sync.vhd diff --git a/lib/JBUS/ghdl/tb_dmac_sync.gtkw b/lib/JBUS/dmac/ghdl/tb_dmac_sync.gtkw similarity index 100% rename from lib/JBUS/ghdl/tb_dmac_sync.gtkw rename to lib/JBUS/dmac/ghdl/tb_dmac_sync.gtkw diff --git a/lib/JBUS/ghdl/tb_dmac_sync.make b/lib/JBUS/dmac/ghdl/tb_dmac_sync.make similarity index 100% rename from lib/JBUS/ghdl/tb_dmac_sync.make rename to lib/JBUS/dmac/ghdl/tb_dmac_sync.make diff --git a/lib/JBUS/sim/tb_dmac.fdo b/lib/JBUS/dmac/sim/tb_dmac.fdo similarity index 100% rename from lib/JBUS/sim/tb_dmac.fdo rename to lib/JBUS/dmac/sim/tb_dmac.fdo diff --git a/lib/JBUS/sim/tb_dmac.wdo b/lib/JBUS/dmac/sim/tb_dmac.wdo similarity index 100% rename from lib/JBUS/sim/tb_dmac.wdo rename to lib/JBUS/dmac/sim/tb_dmac.wdo diff --git a/lib/JBUS/src/dmac/dmac.vhd b/lib/JBUS/dmac/src/dmac.vhd similarity index 100% rename from lib/JBUS/src/dmac/dmac.vhd rename to lib/JBUS/dmac/src/dmac.vhd diff --git a/lib/JBUS/src/dmac/tb_dmac.vhd b/lib/JBUS/dmac/src/tb_dmac.vhd similarity index 100% rename from lib/JBUS/src/dmac/tb_dmac.vhd rename to lib/JBUS/dmac/src/tb_dmac.vhd diff --git a/lib/JBUS/src/flash_port/flash_port_wb.vhd b/lib/JBUS/flash_port/src/flash_port_wb.vhd similarity index 100% rename from lib/JBUS/src/flash_port/flash_port_wb.vhd rename to lib/JBUS/flash_port/src/flash_port_wb.vhd diff --git a/lib/JBUS/src/gpio/gpio_wb.vhd b/lib/JBUS/gpio/src/gpio_wb.vhd similarity index 100% rename from lib/JBUS/src/gpio/gpio_wb.vhd rename to lib/JBUS/gpio/src/gpio_wb.vhd diff --git a/lib/JBUS/ghdl/tb_ram_wb.gtkw b/lib/JBUS/memory/ghdl/tb_ram_wb.gtkw similarity index 100% rename from lib/JBUS/ghdl/tb_ram_wb.gtkw rename to lib/JBUS/memory/ghdl/tb_ram_wb.gtkw diff --git a/lib/JBUS/ghdl/tb_ram_wb.make b/lib/JBUS/memory/ghdl/tb_ram_wb.make similarity index 100% rename from lib/JBUS/ghdl/tb_ram_wb.make rename to lib/JBUS/memory/ghdl/tb_ram_wb.make diff --git a/lib/JBUS/ghdl/tb_rom_wb.gtkw b/lib/JBUS/memory/ghdl/tb_rom_wb.gtkw similarity index 100% rename from lib/JBUS/ghdl/tb_rom_wb.gtkw rename to lib/JBUS/memory/ghdl/tb_rom_wb.gtkw diff --git a/lib/JBUS/ghdl/tb_rom_wb.make b/lib/JBUS/memory/ghdl/tb_rom_wb.make similarity index 100% rename from lib/JBUS/ghdl/tb_rom_wb.make rename to lib/JBUS/memory/ghdl/tb_rom_wb.make diff --git a/lib/JBUS/sim/tb_ram_wb.fdo b/lib/JBUS/memory/sim/tb_ram_wb.fdo similarity index 100% rename from lib/JBUS/sim/tb_ram_wb.fdo rename to lib/JBUS/memory/sim/tb_ram_wb.fdo diff --git a/lib/JBUS/sim/tb_ram_wb.wdo b/lib/JBUS/memory/sim/tb_ram_wb.wdo similarity index 100% rename from lib/JBUS/sim/tb_ram_wb.wdo rename to lib/JBUS/memory/sim/tb_ram_wb.wdo diff --git a/lib/JBUS/sim/tb_rom_wb.fdo b/lib/JBUS/memory/sim/tb_rom_wb.fdo similarity index 100% rename from lib/JBUS/sim/tb_rom_wb.fdo rename to lib/JBUS/memory/sim/tb_rom_wb.fdo diff --git a/lib/JBUS/sim/tb_rom_wb.wdo b/lib/JBUS/memory/sim/tb_rom_wb.wdo similarity index 100% rename from lib/JBUS/sim/tb_rom_wb.wdo rename to lib/JBUS/memory/sim/tb_rom_wb.wdo diff --git a/lib/JBUS/src/memory/ram_wb.vhd b/lib/JBUS/memory/src/ram_wb.vhd similarity index 100% rename from lib/JBUS/src/memory/ram_wb.vhd rename to lib/JBUS/memory/src/ram_wb.vhd diff --git a/lib/JBUS/src/memory/rom_sim.vhd b/lib/JBUS/memory/src/rom_sim.vhd similarity index 100% rename from lib/JBUS/src/memory/rom_sim.vhd rename to lib/JBUS/memory/src/rom_sim.vhd diff --git a/lib/JBUS/src/memory/rom_wb.vhd b/lib/JBUS/memory/src/rom_wb.vhd similarity index 100% rename from lib/JBUS/src/memory/rom_wb.vhd rename to lib/JBUS/memory/src/rom_wb.vhd diff --git a/lib/JBUS/src/memory/tb_ram_wb.vhd b/lib/JBUS/memory/src/tb_ram_wb.vhd similarity index 100% rename from lib/JBUS/src/memory/tb_ram_wb.vhd rename to lib/JBUS/memory/src/tb_ram_wb.vhd diff --git a/lib/JBUS/src/memory/tb_rom_wb.vhd b/lib/JBUS/memory/src/tb_rom_wb.vhd similarity index 100% rename from lib/JBUS/src/memory/tb_rom_wb.vhd rename to lib/JBUS/memory/src/tb_rom_wb.vhd