- removed BUFG for clk_out. It's now in clkgen

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git-svn-id: http://moon:8086/svn/vhdl/trunk@598 cc03376c-175c-47c8-b038-4cd826a8556b

projects/mips_sys/src/mips_sys.vhd

@@ -319,7 +319,6 @@ ARCHITECTURE behavior OF mips_sys IS
 	signal sdram_clk270			: std_logic;
 	signal sdram_clk270var		: std_logic;
 	signal vga_clk				: std_logic;
-	signal vga_clk_prebuf		: std_logic;
 	signal vga_clk_lock			: std_logic;
 	signal rst_in				: std_logic;
 	signal int_timer			: std_logic;
@@ -883,17 +882,10 @@ inst_clkgen: entity work.clkgen
 	(
 		rst			=> rst_in,
 		clk_in		=> CLK_O,
-		clk_out		=> vga_clk_prebuf,
+		clk_out		=> vga_clk,
 		locked		=> vga_clk_lock
 	);
 
-	BUFG_out_clk : BUFG
-	port map
-	(
-		O => vga_clk,     -- Clock buffer output
-		I => vga_clk_prebuf     -- Clock buffer input
-	);
-
 inst_vga_frontend : vga_frontend64
 	GENERIC MAP
 	(