From 57efb02eb630a327be96b24694b442ea935f9aa2 Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Wed, 4 Nov 2009 10:39:59 +0000 Subject: [PATCH] - removed BUFG for clk_out. It's now in clkgen Committed on the Free edition of March Hare Software CVSNT Server. Upgrade to CVS Suite for more features and support: http://march-hare.com/cvsnt/ git-svn-id: http://moon:8086/svn/vhdl/trunk@598 cc03376c-175c-47c8-b038-4cd826a8556b --- projects/mips_sys/src/mips_sys.vhd | 14 +++----------- 1 file changed, 3 insertions(+), 11 deletions(-) diff --git a/projects/mips_sys/src/mips_sys.vhd b/projects/mips_sys/src/mips_sys.vhd index 6795c9b..9458d4f 100644 --- a/projects/mips_sys/src/mips_sys.vhd +++ b/projects/mips_sys/src/mips_sys.vhd @@ -319,7 +319,6 @@ ARCHITECTURE behavior OF mips_sys IS signal sdram_clk270 : std_logic; signal sdram_clk270var : std_logic; signal vga_clk : std_logic; - signal vga_clk_prebuf : std_logic; signal vga_clk_lock : std_logic; signal rst_in : std_logic; signal int_timer : std_logic; @@ -342,8 +341,8 @@ ARCHITECTURE behavior OF mips_sys IS signal arb_gnt : unsigned (ARB_MAX_MASTER-1 downto 0); -- J-Bus signals - signal CLK_O : std_logic; - signal RST_O : std_logic; + signal CLK_O : std_logic; + signal RST_O : std_logic; signal INT : unsigned(5 downto 0); signal MDAT_I : word_t; signal MDAT_O : word_t; @@ -883,17 +882,10 @@ inst_clkgen: entity work.clkgen ( rst => rst_in, clk_in => CLK_O, - clk_out => vga_clk_prebuf, + clk_out => vga_clk, locked => vga_clk_lock ); - BUFG_out_clk : BUFG - port map - ( - O => vga_clk, -- Clock buffer output - I => vga_clk_prebuf -- Clock buffer input - ); - inst_vga_frontend : vga_frontend64 GENERIC MAP (