- added
git-svn-id: http://moon:8086/svn/vhdl/trunk@1422 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
@@ -0,0 +1,89 @@
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--------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 19:34:24 10/23/05
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-- Design Name:
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-- Module Name: debounce - Behavioral
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-- Project Name:
|
||||
-- Target Device:
|
||||
-- Tool versions:
|
||||
-- Description:
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||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
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||||
-- Additional Comments:
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||||
--
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||||
--------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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---- Uncomment the following library declaration if instantiating
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---- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity debounce is
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Generic ( ncyc_latency : integer := 100);
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Port ( rst : in std_logic;
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clk : in std_logic;
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input : in std_logic;
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output : out std_logic);
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end debounce;
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architecture Behavioral of debounce is
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type debounce_state_t is (init_st, wait_st, rel_st);
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signal debounce_cs : debounce_state_t;
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signal debounce_ns : debounce_state_t;
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signal count : integer range 0 to ncyc_latency-1;
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signal input_last : std_logic;
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begin
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debounce_clk: process(rst, clk, debounce_ns, debounce_cs, input)
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begin
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if (rst = '1') then
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count <= 0;
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output <= input;
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input_last <= input;
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else
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if rising_edge(clk) then
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debounce_cs <= debounce_ns;
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if (debounce_cs = wait_st) then
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if (count /= 0) then
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count <= count - 1;
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end if;
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else
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count <= ncyc_latency-1;
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if (debounce_cs = rel_st) then
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output <= input;
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input_last <= input;
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end if;
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end if;
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end if;
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end if;
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end process;
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debounce_in: process(rst, clk, input, input_last, debounce_cs, count)
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begin
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debounce_ns <= debounce_cs;
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case debounce_cs is
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when init_st =>
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if (input /= input_last) then
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debounce_ns <= wait_st;
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end if;
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when wait_st =>
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if (count = 0) then
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debounce_ns <= rel_st;
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end if;
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when others =>
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debounce_ns <= init_st;
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end case;
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end process;
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end Behavioral;
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@@ -0,0 +1,60 @@
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--------------------------------------------------------------------------------
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-- Company:
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||||
-- Engineer:
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||||
--
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||||
-- Create Date: 07:53:41 10/28/05
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-- Design Name:
|
||||
-- Module Name: parity_bitser - Behavioral
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-- Project Name:
|
||||
-- Target Device:
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||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
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||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
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||||
-- Additional Comments:
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||||
--
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||||
--------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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---- Uncomment the following library declaration if instantiating
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---- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity parity_bitser is
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Port ( rst : in std_logic;
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clk : in std_logic;
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srst : in std_logic;
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ce : in std_logic;
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d_in : in std_logic;
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parity : out std_logic);
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end parity_bitser;
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architecture Behavioral of parity_bitser is
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signal parity_i : std_logic;
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begin
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process (rst, srst, clk, ce, d_in)
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begin
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if rst='1' then
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parity_i <= '1';
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elsif clk='1' and clk'event then
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if srst='1' then
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parity_i <= '1';
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elsif ce = '1' and d_in = '1' then
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parity_i <= not parity_i;
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end if;
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end if;
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end process;
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parity <= parity_i;
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end Behavioral;
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@@ -0,0 +1,60 @@
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--------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 13:42:03 10/29/05
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-- Design Name:
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||||
-- Module Name: piso - Behavioral
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-- Project Name:
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||||
-- Target Device:
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||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
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||||
-- Additional Comments:
|
||||
--
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||||
--------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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---- Uncomment the following library declaration if instantiating
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---- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity piso is
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Generic (N : integer := 8);
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Port ( rst : in std_logic;
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clk : in std_logic;
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ce : in std_logic;
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load_en : in std_logic;
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d_in : in std_logic_vector(N-1 downto 0);
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d_out : out std_logic);
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end piso;
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architecture Behavioral of piso is
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signal reg : std_logic_vector(N-1 downto 0);
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begin
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process (rst, clk, ce, reg, load_en, d_in)
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begin
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if rst ='1' then
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reg <= (others => '0');
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elsif load_en = '1' then
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reg <= d_in;
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elsif clk'event and clk='1' then
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if ce = '1' then
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reg <= '0' & reg((N-1) downto 1);
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end if;
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end if;
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d_out <= reg(0);
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end process;
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end Behavioral;
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@@ -0,0 +1,61 @@
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--------------------------------------------------------------------------------
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-- Company:
|
||||
-- Engineer:
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||||
--
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||||
-- Create Date: 18:45:29 10/22/05
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-- Design Name:
|
||||
-- Module Name: prescaler - Behavioral
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||||
-- Project Name:
|
||||
-- Target Device:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
--------------------------------------------------------------------------------
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||||
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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||||
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---- Uncomment the following library declaration if instantiating
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||||
---- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity prescaler is
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Generic (divide : integer := 8);
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Port ( rst : in std_logic;
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clk : in std_logic;
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ce : in std_logic;
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rdy : out std_logic);
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end prescaler;
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architecture Behavioral of prescaler is
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begin
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proc_prescaler: process(rst, clk, ce)
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variable cnt_prescaler : integer range 0 to divide-1;
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begin
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if rst = '1' then
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cnt_prescaler := divide - 1;
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rdy <= '0';
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elsif clk'event and clk='1' then
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if ce = '1' then
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if cnt_prescaler = 0 then
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cnt_prescaler := divide - 1;
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rdy <= '1';
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else
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cnt_prescaler := cnt_prescaler - 1;
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rdy <= '0';
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end if;
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end if;
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end if;
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end process proc_prescaler;
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end Behavioral;
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@@ -0,0 +1,240 @@
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--------------------------------------------------------------------------------
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||||
-- Company:
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||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 18:05:41 10/22/05
|
||||
-- Design Name:
|
||||
-- Module Name: ps2_core - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Device:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
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||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
---- Uncomment the following library declaration if instantiating
|
||||
---- any Xilinx primitives in this code.
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||||
--library UNISIM;
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--use UNISIM.VComponents.all;
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entity ps2_core is
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Generic (f_sys_clk : real := 100.0);
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Port ( rst : in std_logic;
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clk : in std_logic;
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ce : in std_logic;
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||||
d_in : in std_logic_vector(7 downto 0);
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d_out : out std_logic_vector(7 downto 0);
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rdy_in : out std_logic;
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rdy_out : out std_logic;
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write_en : in std_logic;
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read_en : in std_logic;
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ps2_clk : in std_logic;
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ps2_data : in std_logic);
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end ps2_core;
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architecture Behavioral of ps2_core is
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COMPONENT prescaler
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GENERIC (divide : integer);
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PORT(
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rst : IN std_logic;
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clk : IN std_logic;
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ce : IN std_logic;
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||||
rdy : OUT std_logic
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||||
);
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END COMPONENT;
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||||
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COMPONENT timeout_counter
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||||
GENERIC (N : integer);
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PORT(
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rst : IN std_logic;
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clk : IN std_logic;
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ce : IN std_logic;
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||||
load : IN integer range 0 to N-1;
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||||
load_en : IN std_logic;
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||||
rdy : OUT std_logic
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||||
);
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END COMPONENT;
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||||
|
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COMPONENT sipo
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GENERIC (N : integer);
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||||
PORT(
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||||
rst : IN std_logic;
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clk : IN std_logic;
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||||
ce : IN std_logic;
|
||||
d_in : IN std_logic;
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d_out : OUT std_logic_vector(7 downto 0)
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||||
);
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||||
END COMPONENT;
|
||||
|
||||
COMPONENT oneshot
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||||
GENERIC (mode : integer);
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||||
PORT(
|
||||
rst : IN std_logic;
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clk : IN std_logic;
|
||||
input : IN std_logic;
|
||||
output : OUT std_logic
|
||||
);
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END COMPONENT;
|
||||
|
||||
-- Types
|
||||
type read_state_t is (read_start_st, read_data_st, read_parity_st, read_stop_st);
|
||||
|
||||
-- Constant
|
||||
constant prescaler_us : integer := integer(f_sys_clk);
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||||
constant timeout_us : integer := 1000;
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||||
|
||||
-- Signals
|
||||
signal en_us : std_logic;
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signal timeout_load_en : std_logic;
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signal timeout_flag : std_logic;
|
||||
signal read_cs : read_state_t;
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||||
signal read_ns : read_state_t;
|
||||
signal data_cnt_en : std_logic;
|
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signal data_cnt : integer range 0 to 7;
|
||||
signal sipo_en : std_logic;
|
||||
signal data_rdy : std_logic;
|
||||
signal out_reg_ce : std_logic;
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||||
signal sipo_reg : std_logic_vector(7 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
Inst_prescaler: prescaler
|
||||
GENERIC MAP (
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||||
divide => prescaler_us)
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||||
PORT MAP(
|
||||
rst => rst,
|
||||
clk => clk,
|
||||
ce => ce,
|
||||
rdy => en_us
|
||||
);
|
||||
|
||||
Inst_timeout_counter: timeout_counter
|
||||
GENERIC MAP (
|
||||
N => timeout_us)
|
||||
PORT MAP(
|
||||
rst => rst,
|
||||
clk => clk,
|
||||
ce => en_us,
|
||||
load => timeout_us - 1,
|
||||
load_en => timeout_load_en,
|
||||
rdy => timeout_flag
|
||||
);
|
||||
|
||||
Inst_sipo: sipo
|
||||
GENERIC MAP (
|
||||
N => 8)
|
||||
PORT MAP(
|
||||
rst => rst,
|
||||
clk => ps2_clk,
|
||||
ce => sipo_en,
|
||||
d_in => ps2_data,
|
||||
d_out => sipo_reg
|
||||
);
|
||||
|
||||
Inst_oneshot: oneshot
|
||||
GENERIC MAP (
|
||||
mode => 1)
|
||||
PORT MAP(
|
||||
rst => rst,
|
||||
clk => clk,
|
||||
input => data_rdy,
|
||||
output => out_reg_ce
|
||||
);
|
||||
|
||||
-------------------------------------------
|
||||
out_reg: process(rst, clk, out_reg_ce, read_en)
|
||||
begin
|
||||
if rst = '1' then
|
||||
d_out <= (others => '0');
|
||||
rdy_out <= '0';
|
||||
elsif rising_edge(clk) then
|
||||
if out_reg_ce = '1' then
|
||||
d_out <= sipo_reg;
|
||||
rdy_out <= '1';
|
||||
elsif read_en = '1' then
|
||||
rdy_out <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
read_state_clk: process(rst, ps2_clk)
|
||||
begin
|
||||
if rst = '1' then
|
||||
read_cs <= read_start_st;
|
||||
else
|
||||
if falling_edge(ps2_clk) then
|
||||
read_cs <= read_ns;
|
||||
if (data_cnt_en = '1') then
|
||||
if (data_cnt /= 0) then
|
||||
data_cnt <= data_cnt - 1;
|
||||
end if;
|
||||
else
|
||||
data_cnt <= 7;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
read_state_output: process(read_cs)
|
||||
begin
|
||||
|
||||
timeout_load_en <= '0';
|
||||
data_cnt_en <= '0';
|
||||
rdy_in <= '0';
|
||||
sipo_en <= '0';
|
||||
data_rdy <= '0';
|
||||
-- rdy_out <= '0';
|
||||
case (read_cs) is
|
||||
when read_start_st =>
|
||||
data_rdy <= '1';
|
||||
timeout_load_en <= '1';
|
||||
-- rdy_out <= '1';
|
||||
when read_data_st =>
|
||||
sipo_en <= '1';
|
||||
data_cnt_en <= '1';
|
||||
when others => null;
|
||||
end case;
|
||||
end process;
|
||||
|
||||
read_state_decode: process (read_cs, timeout_flag, data_cnt, ps2_data)
|
||||
begin
|
||||
--declare default state for next_state to avoid latches
|
||||
read_ns <= read_cs; --default is to stay in current state
|
||||
--insert statements to decode next_state
|
||||
--below is a simple example
|
||||
case (read_cs) is
|
||||
when read_start_st =>
|
||||
if ps2_data = '0' then
|
||||
read_ns <= read_data_st;
|
||||
end if;
|
||||
when read_data_st =>
|
||||
if timeout_flag = '1' then
|
||||
read_ns <= read_start_st;
|
||||
elsif data_cnt = 0 then
|
||||
read_ns <= read_parity_st;
|
||||
end if;
|
||||
when read_parity_st =>
|
||||
read_ns <= read_stop_st;
|
||||
if timeout_flag = '1' then
|
||||
read_ns <= read_start_st;
|
||||
end if;
|
||||
when read_stop_st =>
|
||||
read_ns <= read_start_st;
|
||||
when others =>
|
||||
read_ns <= read_start_st;
|
||||
end case;
|
||||
end process;
|
||||
|
||||
end Behavioral;
|
||||
@@ -0,0 +1,610 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 18:05:41 10/22/05
|
||||
-- Design Name:
|
||||
-- Module Name: ps2_core - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Device:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
---- Uncomment the following library declaration if instantiating
|
||||
---- any Xilinx primitives in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity ps2_core is
|
||||
Generic (f_sys_clk : real := 100.0);
|
||||
Port ( rst : in std_logic;
|
||||
clk : in std_logic;
|
||||
ce : in std_logic;
|
||||
d_in : in std_logic_vector(7 downto 0);
|
||||
d_out : out std_logic_vector(7 downto 0);
|
||||
input_rdy : out std_logic;
|
||||
output_rdy : out std_logic;
|
||||
write_en : in std_logic;
|
||||
read_en : in std_logic;
|
||||
ps2_clk_in : in std_logic;
|
||||
ps2_data_in : in std_logic;
|
||||
ps2_clk_out : out std_logic;
|
||||
ps2_data_out : out std_logic);
|
||||
|
||||
end ps2_core;
|
||||
|
||||
architecture Behavioral of ps2_core is
|
||||
|
||||
COMPONENT prescaler
|
||||
GENERIC (divide : integer);
|
||||
PORT(
|
||||
rst : IN std_logic;
|
||||
clk : IN std_logic;
|
||||
ce : IN std_logic;
|
||||
rdy : OUT std_logic
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
COMPONENT timeout_counter
|
||||
GENERIC (N : integer);
|
||||
PORT(
|
||||
rst : IN std_logic;
|
||||
clk : IN std_logic;
|
||||
ce : IN std_logic;
|
||||
load : IN integer range 0 to N-1;
|
||||
load_en : IN std_logic;
|
||||
rdy : OUT std_logic
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
COMPONENT sipo
|
||||
GENERIC (N : integer);
|
||||
PORT(
|
||||
rst : IN std_logic;
|
||||
clk : IN std_logic;
|
||||
ce : IN std_logic;
|
||||
d_in : IN std_logic;
|
||||
d_out : OUT std_logic_vector(7 downto 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
COMPONENT piso
|
||||
GENERIC (N : integer);
|
||||
PORT(
|
||||
rst : IN std_logic;
|
||||
clk : IN std_logic;
|
||||
ce : IN std_logic;
|
||||
load_en : IN std_logic;
|
||||
d_in : IN std_logic_vector(7 downto 0);
|
||||
d_out : OUT std_logic
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
COMPONENT parity_bitser
|
||||
PORT(
|
||||
rst : IN std_logic;
|
||||
clk : IN std_logic;
|
||||
srst : IN std_logic;
|
||||
ce : IN std_logic;
|
||||
d_in : IN std_logic;
|
||||
parity : OUT std_logic
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
COMPONENT oneshot
|
||||
GENERIC (mode : integer);
|
||||
PORT(
|
||||
rst : IN std_logic;
|
||||
clk : IN std_logic;
|
||||
input : IN std_logic;
|
||||
output : OUT std_logic
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
|
||||
-- Types
|
||||
type line_state_rx_t is (start_wait_st, start_trans_st, start_sample_st,
|
||||
data_wait_st, data_trans_st, data_sample_st,
|
||||
parity_wait_st, parity_trans_st, parity_sample_st,
|
||||
stop_wait_st, stop_trans_st, stop_sample_st,
|
||||
valid_st);
|
||||
|
||||
type line_state_tx_t is (tx_idle_st, tx_clock_assert_st, tx_start_latency_st,
|
||||
tx_start_assert_st, tx_clock_release_st, tx_dev_trans_st,
|
||||
tx_data_wait_st, tx_data_trans_st, tx_data_sample_st,
|
||||
tx_parity_update_st, tx_dev_wait_st,
|
||||
tx_parity_wait_st, tx_parity_trans_st, tx_parity_sample_st,
|
||||
tx_stop_wait_st, tx_stop_trans_st, tx_stop_sample_st,
|
||||
tx_ack_trans_st, tx_ack_sample_st, tx_valid_st);
|
||||
|
||||
-- Constant
|
||||
constant prescaler_us : integer := f_sys_clk/1E6;
|
||||
constant timeout_us : integer := 15000;
|
||||
constant time_clock_assert : integer := 120;
|
||||
|
||||
-- Signals
|
||||
signal en_us : std_logic;
|
||||
signal timeout_load_en : std_logic;
|
||||
signal timeout_en : std_logic;
|
||||
signal timeout_flag : std_logic;
|
||||
|
||||
signal timeout_tx_load_en : std_logic;
|
||||
signal timeout_tx_en : std_logic;
|
||||
signal timeout_tx_flag : std_logic;
|
||||
signal timeval_tx : integer := time_clock_assert-1;
|
||||
|
||||
signal read_cs : line_state_rx_t;
|
||||
signal read_ns : line_state_rx_t;
|
||||
signal write_cs : line_state_tx_t;
|
||||
signal write_ns : line_state_tx_t;
|
||||
|
||||
signal data_cnt_en : std_logic;
|
||||
signal data_cnt_rst : std_logic;
|
||||
signal data_cnt : integer range 0 to 7;
|
||||
|
||||
signal data_cnt_tx_en : std_logic;
|
||||
signal data_cnt_tx_rst : std_logic;
|
||||
signal data_cnt_tx : integer range 0 to 7;
|
||||
|
||||
signal sipo_en : std_logic;
|
||||
signal piso_en : std_logic;
|
||||
signal piso_out : std_logic;
|
||||
signal piso_load_en : std_logic;
|
||||
signal rx_en : std_logic;
|
||||
signal tx_en : std_logic;
|
||||
signal rx_busy : std_logic;
|
||||
signal tx_busy : std_logic;
|
||||
signal rx_rdy : std_logic;
|
||||
signal tx_rdy : std_logic;
|
||||
signal tx_req : std_logic;
|
||||
signal rx_reg : std_logic_vector(7 downto 0);
|
||||
signal tx_reg : std_logic_vector(7 downto 0);
|
||||
|
||||
signal parity_rst : std_logic;
|
||||
signal parity_en : std_logic;
|
||||
signal parity : std_logic;
|
||||
signal parity_tx_rst : std_logic;
|
||||
signal parity_tx_en : std_logic;
|
||||
signal parity_tx : std_logic;
|
||||
|
||||
begin
|
||||
|
||||
Inst_prescaler: prescaler
|
||||
GENERIC MAP (
|
||||
divide => prescaler_us)
|
||||
PORT MAP(
|
||||
rst => rst,
|
||||
clk => clk,
|
||||
ce => ce,
|
||||
rdy => en_us
|
||||
);
|
||||
|
||||
Inst_timeout_counter_rx: timeout_counter
|
||||
GENERIC MAP (
|
||||
N => timeout_us)
|
||||
PORT MAP(
|
||||
rst => rst,
|
||||
clk => clk,
|
||||
ce => timeout_en,
|
||||
load => timeout_us - 1,
|
||||
load_en => timeout_load_en,
|
||||
rdy => timeout_flag
|
||||
);
|
||||
|
||||
Inst_timeout_counter_tx: timeout_counter
|
||||
GENERIC MAP (
|
||||
N => timeout_us)
|
||||
PORT MAP(
|
||||
rst => rst,
|
||||
clk => clk,
|
||||
ce => timeout_tx_en,
|
||||
load => timeval_tx,
|
||||
load_en => timeout_tx_load_en,
|
||||
rdy => timeout_tx_flag
|
||||
);
|
||||
|
||||
Inst_sipo: sipo
|
||||
GENERIC MAP (
|
||||
N => 8)
|
||||
PORT MAP(
|
||||
rst => rst,
|
||||
clk => clk,
|
||||
ce => sipo_en,
|
||||
d_in => ps2_data_in,
|
||||
d_out => rx_reg
|
||||
);
|
||||
|
||||
Inst_piso: piso
|
||||
GENERIC MAP (
|
||||
N => 8)
|
||||
PORT MAP(
|
||||
rst => rst,
|
||||
clk => clk,
|
||||
ce => piso_en,
|
||||
load_en => piso_load_en,
|
||||
d_in => tx_reg,
|
||||
d_out => piso_out
|
||||
);
|
||||
|
||||
Inst_parity_bitser_rx: parity_bitser
|
||||
PORT MAP(
|
||||
rst => rst,
|
||||
clk => clk,
|
||||
srst => parity_rst,
|
||||
ce => parity_en,
|
||||
d_in => ps2_data_in,
|
||||
parity => parity
|
||||
);
|
||||
|
||||
Inst_parity_bitser_tx: parity_bitser
|
||||
PORT MAP(
|
||||
rst => rst,
|
||||
clk => clk,
|
||||
srst => parity_tx_rst,
|
||||
ce => parity_tx_en,
|
||||
d_in => piso_out,
|
||||
parity => parity_tx
|
||||
);
|
||||
|
||||
|
||||
-------------------------------------------
|
||||
tx_en <= tx_req and (not rx_busy);
|
||||
rx_en <= not tx_busy;
|
||||
|
||||
-------------------------------------------
|
||||
out_reg: process(rst, clk, rx_rdy, read_en)
|
||||
begin
|
||||
if rst = '1' then
|
||||
d_out <= (others => '0');
|
||||
output_rdy <= '0';
|
||||
elsif rising_edge(clk) then
|
||||
if rx_rdy = '1' then
|
||||
d_out <= rx_reg;
|
||||
output_rdy <= '1';
|
||||
elsif read_en = '1' then
|
||||
output_rdy <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
in_reg: process(rst, clk, piso_load_en, write_en)
|
||||
begin
|
||||
if rst = '1' then
|
||||
input_rdy <= '1';
|
||||
tx_req <= '0';
|
||||
elsif rising_edge(clk) then
|
||||
if piso_load_en = '1' then
|
||||
tx_reg <= d_in;
|
||||
input_rdy <= '1';
|
||||
tx_req <= '0';
|
||||
elsif write_en = '1' then
|
||||
input_rdy <= '0';
|
||||
tx_req <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-------------------------------------------
|
||||
read_state_clk: process(rst, clk)
|
||||
begin
|
||||
if rst = '1' then
|
||||
read_cs <= start_wait_st;
|
||||
else
|
||||
if rising_edge(clk) then
|
||||
read_cs <= read_ns;
|
||||
if (data_cnt_rst = '1') then
|
||||
data_cnt <= 7;
|
||||
elsif (data_cnt_en = '1') then
|
||||
if (data_cnt /= 0) then
|
||||
data_cnt <= data_cnt - 1;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-------------------------------------------
|
||||
write_state_clk: process(rst, clk)
|
||||
begin
|
||||
if rst = '1' then
|
||||
write_cs <= tx_idle_st;
|
||||
else
|
||||
if rising_edge(clk) then
|
||||
write_cs <= write_ns;
|
||||
if (data_cnt_tx_rst = '1') then
|
||||
data_cnt_tx <= 7;
|
||||
elsif (data_cnt_tx_en = '1') then
|
||||
if (data_cnt_tx /= 0) then
|
||||
data_cnt_tx <= data_cnt_tx - 1;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-------------------------------------------
|
||||
read_state_output: process(read_cs, en_us)
|
||||
begin
|
||||
|
||||
timeout_load_en <= '0';
|
||||
timeout_en <= en_us;
|
||||
data_cnt_en <= '0';
|
||||
data_cnt_rst <= '0';
|
||||
sipo_en <= '0';
|
||||
rx_rdy <= '0';
|
||||
parity_en <= '0';
|
||||
parity_rst <= '0';
|
||||
rx_busy <= '1';
|
||||
case (read_cs) is
|
||||
when start_wait_st =>
|
||||
timeout_load_en <= '1';
|
||||
timeout_en <= '0';
|
||||
rx_busy <= '0';
|
||||
when start_sample_st =>
|
||||
data_cnt_rst <= '1';
|
||||
parity_rst <= '1';
|
||||
timeout_load_en <= '1';
|
||||
when data_sample_st =>
|
||||
data_cnt_en <= '1';
|
||||
parity_en <= '1';
|
||||
sipo_en <= '1';
|
||||
timeout_load_en <= '1';
|
||||
when parity_sample_st =>
|
||||
timeout_load_en <= '1';
|
||||
parity_en <= '1';
|
||||
when valid_st =>
|
||||
rx_busy <= '0';
|
||||
rx_rdy <= '1';
|
||||
when others => null;
|
||||
end case;
|
||||
end process;
|
||||
|
||||
read_state_decode: process (read_cs, timeout_flag, rx_en, data_cnt, ps2_data_in, ps2_clk_in)
|
||||
begin
|
||||
--declare default state for next_state to avoid latches
|
||||
read_ns <= read_cs; --default is to stay in current state
|
||||
--insert statements to decode next_state
|
||||
--below is a simple example
|
||||
case (read_cs) is
|
||||
when start_wait_st =>
|
||||
if ps2_data_in = '0' and ps2_clk_in = '1' and rx_en = '1' then
|
||||
read_ns <= start_trans_st;
|
||||
end if;
|
||||
when start_trans_st =>
|
||||
if timeout_flag = '1' then
|
||||
read_ns <= start_wait_st;
|
||||
elsif ps2_data_in = '0' and ps2_clk_in = '0' then
|
||||
read_ns <= start_sample_st;
|
||||
end if;
|
||||
when start_sample_st =>
|
||||
read_ns <= data_wait_st;
|
||||
-- Wait data change
|
||||
when data_wait_st =>
|
||||
if timeout_flag = '1' then
|
||||
read_ns <= start_wait_st;
|
||||
elsif ps2_clk_in = '1' then
|
||||
read_ns <= data_trans_st;
|
||||
end if;
|
||||
-- Wait data trans
|
||||
when data_trans_st =>
|
||||
if timeout_flag = '1' then
|
||||
read_ns <= start_wait_st;
|
||||
elsif ps2_clk_in = '0' then
|
||||
read_ns <= data_sample_st;
|
||||
end if;
|
||||
-- Data sample
|
||||
when data_sample_st =>
|
||||
read_ns <= data_wait_st;
|
||||
if data_cnt = 0 then
|
||||
read_ns <= parity_wait_st;
|
||||
end if;
|
||||
when parity_wait_st =>
|
||||
if timeout_flag = '1' then
|
||||
read_ns <= start_wait_st;
|
||||
elsif ps2_clk_in = '1' then
|
||||
read_ns <= parity_trans_st;
|
||||
end if;
|
||||
when parity_trans_st =>
|
||||
if timeout_flag = '1' then
|
||||
read_ns <= start_wait_st;
|
||||
elsif ps2_clk_in = '0' then
|
||||
read_ns <= parity_sample_st;
|
||||
end if;
|
||||
when parity_sample_st =>
|
||||
read_ns <= stop_wait_st;
|
||||
when stop_wait_st =>
|
||||
if timeout_flag = '1' then
|
||||
read_ns <= start_wait_st;
|
||||
elsif ps2_clk_in = '1' then
|
||||
read_ns <= stop_trans_st;
|
||||
end if;
|
||||
when stop_trans_st =>
|
||||
if timeout_flag = '1' then
|
||||
read_ns <= start_wait_st;
|
||||
elsif ps2_clk_in = '0' and ps2_data_in = '1' then
|
||||
read_ns <= stop_sample_st;
|
||||
end if;
|
||||
when stop_sample_st =>
|
||||
if timeout_flag = '1' then
|
||||
read_ns <= start_wait_st;
|
||||
elsif ps2_clk_in = '1' then
|
||||
read_ns <= valid_st;
|
||||
end if;
|
||||
when valid_st =>
|
||||
read_ns <= start_wait_st;
|
||||
when others =>
|
||||
read_ns <= start_wait_st;
|
||||
end case;
|
||||
end process;
|
||||
|
||||
-------------------------------------------
|
||||
write_state_output: process(write_cs, en_us, piso_out, parity_tx)
|
||||
begin
|
||||
|
||||
timeout_tx_load_en <= '0';
|
||||
timeout_tx_en <= en_us;
|
||||
tx_rdy <= '0';
|
||||
tx_busy <= '1';
|
||||
piso_load_en <= '0';
|
||||
ps2_clk_out <= '1';
|
||||
ps2_data_out <= '1';
|
||||
piso_en <= '0';
|
||||
timeval_tx <= time_clock_assert - 1;
|
||||
data_cnt_tx_en <= '0';
|
||||
data_cnt_tx_rst <= '0';
|
||||
parity_tx_rst <= '0';
|
||||
parity_tx_en <= '0';
|
||||
case (write_cs) is
|
||||
when tx_idle_st =>
|
||||
tx_busy <= '0';
|
||||
timeout_tx_load_en <= '1';
|
||||
timeout_tx_en <= '0';
|
||||
when tx_clock_assert_st =>
|
||||
parity_tx_rst <= '1';
|
||||
piso_load_en <= '1';
|
||||
data_cnt_tx_rst <= '1';
|
||||
ps2_clk_out <= '0';
|
||||
when tx_start_assert_st =>
|
||||
ps2_clk_out <= '0';
|
||||
ps2_data_out <= '0';
|
||||
when tx_clock_release_st =>
|
||||
ps2_data_out <= '0';
|
||||
timeout_tx_load_en <= '1';
|
||||
timeval_tx <= timeout_us - 1;
|
||||
when tx_dev_wait_st =>
|
||||
ps2_data_out <= '0';
|
||||
when tx_dev_trans_st =>
|
||||
ps2_data_out <= '0';
|
||||
timeout_tx_load_en <= '1';
|
||||
timeval_tx <= timeout_us - 1;
|
||||
when tx_data_wait_st =>
|
||||
ps2_data_out <= piso_out;
|
||||
when tx_data_trans_st =>
|
||||
data_cnt_tx_en <= '1';
|
||||
ps2_data_out <= piso_out;
|
||||
piso_en <= '1';
|
||||
timeout_tx_load_en <= '1';
|
||||
timeval_tx <= timeout_us - 1;
|
||||
parity_tx_en <= '1';
|
||||
when tx_data_sample_st =>
|
||||
ps2_data_out <= piso_out;
|
||||
when tx_parity_update_st =>
|
||||
parity_tx_en <= '1';
|
||||
ps2_data_out <= piso_out;
|
||||
when tx_parity_sample_st =>
|
||||
ps2_data_out <= parity_tx;
|
||||
when tx_parity_wait_st =>
|
||||
ps2_data_out <= parity_tx;
|
||||
when tx_parity_trans_st =>
|
||||
ps2_data_out <= piso_out;
|
||||
timeout_tx_load_en <= '1';
|
||||
timeval_tx <= timeout_us - 1;
|
||||
when tx_valid_st =>
|
||||
tx_rdy <= '1';
|
||||
when others => null;
|
||||
end case;
|
||||
end process;
|
||||
|
||||
write_state_decode: process (write_cs, tx_en, data_cnt_tx, timeout_tx_flag, ps2_data_in, ps2_clk_in)
|
||||
begin
|
||||
--declare default state for next_state to avoid latches
|
||||
write_ns <= write_cs; --default is to stay in current state
|
||||
--insert statements to decode next_state
|
||||
--below is a simple example
|
||||
case (write_cs) is
|
||||
when tx_idle_st =>
|
||||
if tx_en = '1' then
|
||||
write_ns <= tx_clock_assert_st;
|
||||
end if;
|
||||
when tx_clock_assert_st =>
|
||||
if timeout_tx_flag = '1' then
|
||||
write_ns <= tx_start_assert_st;
|
||||
end if;
|
||||
when tx_start_assert_st =>
|
||||
write_ns <= tx_clock_release_st;
|
||||
when tx_clock_release_st =>
|
||||
write_ns <= tx_dev_wait_st;
|
||||
when tx_dev_wait_st =>
|
||||
if timeout_tx_flag = '1' then
|
||||
write_ns <= tx_idle_st;
|
||||
elsif ps2_clk_in = '1' then
|
||||
write_ns <= tx_dev_trans_st;
|
||||
end if;
|
||||
when tx_dev_trans_st =>
|
||||
if timeout_tx_flag = '1' then
|
||||
write_ns <= tx_idle_st;
|
||||
elsif ps2_clk_in = '0' then
|
||||
write_ns <= tx_data_wait_st;
|
||||
end if;
|
||||
when tx_data_wait_st =>
|
||||
if timeout_tx_flag = '1' then
|
||||
write_ns <= tx_idle_st;
|
||||
elsif ps2_clk_in = '1' then
|
||||
write_ns <= tx_data_sample_st;
|
||||
end if;
|
||||
when tx_data_sample_st =>
|
||||
if timeout_tx_flag = '1' then
|
||||
write_ns <= tx_idle_st;
|
||||
elsif ps2_clk_in = '0' then
|
||||
write_ns <= tx_data_trans_st;
|
||||
if (data_cnt_tx = 0) then
|
||||
write_ns <= tx_parity_update_st;
|
||||
end if;
|
||||
end if;
|
||||
when tx_data_trans_st =>
|
||||
write_ns <= tx_data_wait_st;
|
||||
when tx_parity_update_st =>
|
||||
write_ns <= tx_parity_trans_st;
|
||||
when tx_parity_trans_st =>
|
||||
write_ns <= tx_parity_wait_st;
|
||||
when tx_parity_wait_st =>
|
||||
if timeout_tx_flag = '1' then
|
||||
write_ns <= tx_idle_st;
|
||||
elsif ps2_clk_in = '1' then
|
||||
write_ns <= tx_parity_sample_st;
|
||||
end if;
|
||||
when tx_parity_sample_st =>
|
||||
if timeout_tx_flag = '1' then
|
||||
write_ns <= tx_idle_st;
|
||||
elsif ps2_clk_in = '0' then
|
||||
write_ns <= tx_stop_trans_st;
|
||||
end if;
|
||||
when tx_stop_trans_st =>
|
||||
write_ns <= tx_stop_wait_st;
|
||||
when tx_stop_wait_st =>
|
||||
if timeout_tx_flag = '1' then
|
||||
write_ns <= tx_idle_st;
|
||||
elsif ps2_clk_in = '1' then
|
||||
write_ns <= tx_ack_trans_st;
|
||||
end if;
|
||||
when tx_ack_trans_st =>
|
||||
if timeout_tx_flag = '1' then
|
||||
write_ns <= tx_idle_st;
|
||||
elsif ps2_clk_in = '0' and ps2_data_in = '0' then
|
||||
write_ns <= tx_ack_sample_st;
|
||||
end if;
|
||||
when tx_ack_sample_st =>
|
||||
if timeout_tx_flag = '1' then
|
||||
write_ns <= tx_idle_st;
|
||||
elsif ps2_clk_in = '1' and ps2_data_in = '1' then
|
||||
write_ns <= tx_valid_st;
|
||||
end if;
|
||||
when others =>
|
||||
write_ns <= tx_idle_st;
|
||||
end case;
|
||||
end process;
|
||||
|
||||
-------------------------------------------
|
||||
end Behavioral;
|
||||
@@ -0,0 +1,106 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 20:52:44 10/26/05
|
||||
-- Design Name:
|
||||
-- Module Name: ps2_phy - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Device:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
---- Uncomment the following library declaration if instantiating
|
||||
---- any Xilinx primitives in this code.
|
||||
library UNISIM;
|
||||
use UNISIM.VComponents.all;
|
||||
|
||||
entity ps2_phy is
|
||||
Port ( rst : in std_logic;
|
||||
clk : in std_logic;
|
||||
ps2_clk : inout std_logic;
|
||||
ps2_data : inout std_logic;
|
||||
rx_clk : out std_logic;
|
||||
rx_data : out std_logic;
|
||||
tx_clk : in std_logic;
|
||||
tx_data : in std_logic);
|
||||
end ps2_phy;
|
||||
|
||||
architecture Behavioral of ps2_phy is
|
||||
|
||||
COMPONENT debounce
|
||||
GENERIC (ncyc_latency : integer);
|
||||
PORT(
|
||||
rst : IN std_logic;
|
||||
clk : IN std_logic;
|
||||
input : IN std_logic;
|
||||
output : OUT std_logic
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
signal clk_in : std_logic;
|
||||
signal data_in : std_logic;
|
||||
|
||||
begin
|
||||
|
||||
Inst_debounce_clk: debounce
|
||||
GENERIC MAP (
|
||||
ncyc_latency => 8)
|
||||
PORT MAP(
|
||||
rst => rst,
|
||||
clk => clk,
|
||||
input => clk_in,
|
||||
output => rx_clk
|
||||
);
|
||||
|
||||
Inst_debounce_data: debounce
|
||||
GENERIC MAP (
|
||||
ncyc_latency => 8)
|
||||
PORT MAP(
|
||||
rst => rst,
|
||||
clk => clk,
|
||||
input => data_in,
|
||||
output => rx_data
|
||||
);
|
||||
|
||||
IOBUF_inst_ps2_clk : IOBUF
|
||||
generic map (
|
||||
DRIVE => 2,
|
||||
IBUF_DELAY_VALUE => "0", -- Specify the amount of added input delay for buffer, "0"-"16" (Spartan-3E only)
|
||||
IFD_DELAY_VALUE => "AUTO", -- Specify the amount of added delay for input register, "AUTO", "0"-"8" (Spartan-3E only)
|
||||
IOSTANDARD => "DEFAULT",
|
||||
SLEW => "SLOW")
|
||||
port map (
|
||||
O => clk_in, -- Buffer output
|
||||
IO => ps2_clk, -- Buffer inout port (connect directly to top-level port)
|
||||
I => tx_clk, -- Buffer input
|
||||
T => tx_clk -- 3-state enable input
|
||||
);
|
||||
|
||||
IOBUF_inst_ps2_data : IOBUF
|
||||
generic map (
|
||||
DRIVE => 2,
|
||||
IBUF_DELAY_VALUE => "0", -- Specify the amount of added input delay for buffer, "0"-"16" (Spartan-3E only)
|
||||
IFD_DELAY_VALUE => "AUTO", -- Specify the amount of added delay for input register, "AUTO", "0"-"8" (Spartan-3E only)
|
||||
IOSTANDARD => "DEFAULT",
|
||||
SLEW => "SLOW")
|
||||
port map (
|
||||
O => data_in, -- Buffer output
|
||||
IO => ps2_data, -- Buffer inout port (connect directly to top-level port)
|
||||
I => tx_data, -- Buffer input
|
||||
T => tx_data -- 3-state enable input
|
||||
);
|
||||
|
||||
end Behavioral;
|
||||
@@ -0,0 +1 @@
|
||||
DRC detected 0 errors and 0 warnings.
|
||||
@@ -0,0 +1,199 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 15:10:16 10/22/05
|
||||
-- Design Name:
|
||||
-- Module Name: ps2if_top - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Device:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
---- Uncomment the following library declaration if instantiating
|
||||
---- any Xilinx primitives in this code.
|
||||
library UNISIM;
|
||||
use UNISIM.VComponents.all;
|
||||
|
||||
entity ps2if_top is
|
||||
Port ( sys_rst_n_in : in std_logic;
|
||||
sys_clk_in : in std_logic;
|
||||
ps2_mouse_clk : inout std_logic;
|
||||
ps2_mouse_data : inout std_logic;
|
||||
sys_rx : in std_logic;
|
||||
sys_tx : out std_logic;
|
||||
led : out std_logic_vector(3 downto 0));
|
||||
end ps2if_top;
|
||||
|
||||
architecture Behavioral of ps2if_top is
|
||||
|
||||
|
||||
COMPONENT ps2_phy
|
||||
PORT(
|
||||
rst : IN std_logic;
|
||||
clk : IN std_logic;
|
||||
tx_clk : IN std_logic;
|
||||
tx_data : IN std_logic;
|
||||
ps2_clk : INOUT std_logic;
|
||||
ps2_data : INOUT std_logic;
|
||||
rx_clk : OUT std_logic;
|
||||
rx_data : OUT std_logic
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
COMPONENT ps2_core
|
||||
GENERIC(f_sys_clk : integer);
|
||||
PORT(
|
||||
rst : IN std_logic;
|
||||
clk : IN std_logic;
|
||||
ce : IN std_logic;
|
||||
d_in : IN std_logic_vector(7 downto 0);
|
||||
write_en : IN std_logic;
|
||||
read_en : IN std_logic;
|
||||
ps2_clk_in : IN std_logic;
|
||||
ps2_data_in : IN std_logic;
|
||||
d_out : OUT std_logic_vector(7 downto 0);
|
||||
input_rdy : OUT std_logic;
|
||||
output_rdy : OUT std_logic;
|
||||
ps2_clk_out : OUT std_logic;
|
||||
ps2_data_out : OUT std_logic
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
COMPONENT uart_rx
|
||||
PORT(
|
||||
serial_in : IN std_logic;
|
||||
read_buffer : IN std_logic;
|
||||
reset_buffer : IN std_logic;
|
||||
en_16_x_baud : IN std_logic;
|
||||
clk : IN std_logic;
|
||||
data_out : OUT std_logic_vector(7 downto 0);
|
||||
buffer_data_present : OUT std_logic;
|
||||
buffer_full : OUT std_logic;
|
||||
buffer_half_full : OUT std_logic
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
COMPONENT uart_tx
|
||||
PORT(
|
||||
data_in : IN std_logic_vector(7 downto 0);
|
||||
write_buffer : IN std_logic;
|
||||
reset_buffer : IN std_logic;
|
||||
en_16_x_baud : IN std_logic;
|
||||
clk : IN std_logic;
|
||||
serial_out : OUT std_logic;
|
||||
buffer_full : OUT std_logic;
|
||||
buffer_half_full : OUT std_logic
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
constant f_sys_clk_c : real := 100.0;
|
||||
constant uart_baud_c : integer := 115200;
|
||||
constant uart_count_c : integer := integer(1.0E6*f_sys_clk_c)/(16*uart_baud_c);
|
||||
|
||||
signal rst : std_logic;
|
||||
signal clk_in : std_logic;
|
||||
signal clk_out : std_logic;
|
||||
signal data_in : std_logic;
|
||||
signal data_out : std_logic;
|
||||
signal ps2_core_data_out : std_logic_vector(7 downto 0);
|
||||
signal ps2_core_data_in : std_logic_vector(7 downto 0);
|
||||
signal ps2_core_data_out_rdy : std_logic;
|
||||
signal ps2_core_data_in_rdy : std_logic;
|
||||
signal ps2_core_write_en : std_logic;
|
||||
signal uart_en_16_x_baud : std_logic;
|
||||
signal uart_tx_i : std_logic;
|
||||
|
||||
begin
|
||||
|
||||
Inst_ps2_phy: ps2_phy
|
||||
PORT MAP(
|
||||
rst => rst,
|
||||
clk => sys_clk_in,
|
||||
ps2_clk => ps2_mouse_clk,
|
||||
ps2_data => ps2_mouse_data,
|
||||
rx_clk => clk_in,
|
||||
rx_data => data_in,
|
||||
tx_clk => clk_out,
|
||||
tx_data => data_out
|
||||
);
|
||||
|
||||
Inst_ps2_core: ps2_core
|
||||
GENERIC MAP (
|
||||
f_sys_clk => f_sys_clk_c)
|
||||
PORT MAP(
|
||||
rst => rst,
|
||||
clk => sys_clk_in,
|
||||
ce => '1',
|
||||
d_in => ps2_core_data_in,
|
||||
d_out => ps2_core_data_out,
|
||||
input_rdy => ps2_core_data_in_rdy,
|
||||
output_rdy => ps2_core_data_out_rdy,
|
||||
write_en => ps2_core_write_en,
|
||||
read_en => '1',
|
||||
ps2_clk_in => clk_in,
|
||||
ps2_data_in => data_in,
|
||||
ps2_clk_out => clk_out,
|
||||
ps2_data_out => data_out
|
||||
);
|
||||
|
||||
Inst_uart_rx: uart_rx
|
||||
PORT MAP(
|
||||
serial_in => sys_rx,
|
||||
data_out => ps2_core_data_in,
|
||||
read_buffer => ps2_core_data_in_rdy,
|
||||
reset_buffer => rst,
|
||||
en_16_x_baud => uart_en_16_x_baud,
|
||||
buffer_data_present => ps2_core_write_en,
|
||||
buffer_full => open,
|
||||
buffer_half_full => open,
|
||||
clk => sys_clk_in
|
||||
);
|
||||
|
||||
Inst_uart_tx: uart_tx
|
||||
PORT MAP(
|
||||
data_in => ps2_core_data_out,
|
||||
write_buffer => ps2_core_data_out_rdy,
|
||||
reset_buffer => rst,
|
||||
en_16_x_baud => uart_en_16_x_baud,
|
||||
serial_out => uart_tx_i,
|
||||
buffer_full => open,
|
||||
buffer_half_full => open,
|
||||
clk => sys_clk_in
|
||||
);
|
||||
|
||||
|
||||
baud_timer: process(sys_clk_in)
|
||||
variable baud_count : integer range 0 to uart_count_c-1;
|
||||
begin
|
||||
if sys_clk_in'event and sys_clk_in='1' then
|
||||
if baud_count=uart_count_c-1 then
|
||||
baud_count := 0;
|
||||
uart_en_16_x_baud <= '1';
|
||||
else
|
||||
baud_count := baud_count + 1;
|
||||
uart_en_16_x_baud <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end process baud_timer;
|
||||
|
||||
rst <= not sys_rst_n_in;
|
||||
sys_tx <= uart_tx_i;
|
||||
|
||||
led(0) <= not clk_in;
|
||||
led(1) <= not data_in;
|
||||
led(2) <= not clk_out;
|
||||
led(3) <= not data_out;
|
||||
end Behavioral;
|
||||
@@ -0,0 +1,698 @@
|
||||
Release 8.1.03i - par I.27
|
||||
Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
|
||||
|
||||
Thu Jul 06 21:10:17 2006
|
||||
|
||||
|
||||
INFO: The IO information is provided in three file formats as part of the Place and Route (PAR) process. These formats are:
|
||||
1. The <design name>_pad.txt file (this file) designed to provide information on IO usage in a human readable ASCII text format viewable through common text editors.
|
||||
2. The <design namd>_pad.csv file for use with spreadsheet programs such as MS Excel. This file can also be read by PACE to communicate post PAR IO information.
|
||||
3. The <design name>.pad file designed for parsing by customers. It uses the "|" as a data field separator.
|
||||
|
||||
INPUT FILE: ps2if_top_map.ncd
|
||||
OUTPUT FILE: ps2if_top_pad.txt
|
||||
PART TYPE: xc4vsx35
|
||||
SPEED GRADE: -10
|
||||
PACKAGE: ff668
|
||||
|
||||
Pinout by Pin Number:
|
||||
|
||||
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
|Pin Number|Signal Name |Pin Usage|Pin Name |Direction|IO Standard|IO Bank Number|Drive (mA)|Slew Rate|Termination|IOB Delay|Voltage |Constraint|DCI Value|IO Register|Signal Integrity|
|
||||
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
|A2 | | |GND | | | | | | | | | | | | |
|
||||
|A3 | |IOBM |IO_L14P_6 |UNUSED | |6 | | | | | | | | | |
|
||||
|A4 | |IOBM |IO_L15P_6 |UNUSED | |6 | | | | | | | | | |
|
||||
|A5 | |IOBS |IO_L6N_6 |UNUSED | |6 | | | | | | | | | |
|
||||
|A6 | |IOBM |IO_L6P_6 |UNUSED | |6 | | | | | | | | | |
|
||||
|A7 | |IOBS |IO_L3N_6 |UNUSED | |6 | | | | | | | | | |
|
||||
|A8 | |IOBM |IO_L3P_6 |UNUSED | |6 | | | | | | | | | |
|
||||
|A9 | |IOBM |IO_L13P_6 |UNUSED | |6 | | | | | | | | | |
|
||||
|A10 | |LOWCAPIOB|IO_L6P_GC_LC_3 |UNUSED | |3 | | | | | | | | | |
|
||||
|A11 |led<2> |IOB |IO_L2N_GC_VRP_LC_3 |OUTPUT |LVCMOS25 |3 |2 |SLOW |NONE** | | |LOCATED | |NO |NONE |
|
||||
|A12 |led<3> |IOB |IO_L2P_GC_VRN_LC_3 |OUTPUT |LVCMOS25 |3 |2 |SLOW |NONE** | | |LOCATED | |NO |NONE |
|
||||
|A13 | | |GND | | | | | | | | | | | | |
|
||||
|A14 | | |GND | | | | | | | | | | | | |
|
||||
|A15 | |LOWCAPIOB|IO_L5N_GC_LC_3 |UNUSED | |3 | | | | | | | | | |
|
||||
|A16 | |LOWCAPIOB|IO_L5P_GC_LC_3 |UNUSED | |3 | | | | | | | | | |
|
||||
|A17 | |LOWCAPIOB|IO_L7N_GC_LC_3 |UNUSED | |3 | | | | | | | | | |
|
||||
|A18 | |IOBS |IO_L3N_5 |UNUSED | |5 | | | | | | | | | |
|
||||
|A19 | |IOBS |IO_L13N_5 |UNUSED | |5 | | | | | | | | | |
|
||||
|A20 | |IOBM |IO_L13P_5 |UNUSED | |5 | | | | | | | | | |
|
||||
|A21 | |IOBS |IO_L15N_5 |UNUSED | |5 | | | | | | | | | |
|
||||
|A22 | |IOBM |IO_L15P_5 |UNUSED | |5 | | | | | | | | | |
|
||||
|A23 | |LOWCAPIOB|IO_L8N_CC_LC_5 |UNUSED | |5 | | | | | | | | | |
|
||||
|A24 | |LOWCAPIOB|IO_L8P_CC_LC_5 |UNUSED | |5 | | | | | | | | | |
|
||||
|A25 | | |GND | | | | | | | | | | | | |
|
||||
|AA1 | |IOBS |IO_L10N_8 |UNUSED | |8 | | | | | | | | | |
|
||||
|AA2 | | |VCCO_8 | | |8 | | | | |3.30 | | | | |
|
||||
|AA3 | |IOBS |IO_L7N_8 |UNUSED | |8 | | | | | | | | | |
|
||||
|AA4 | |IOBM |IO_L7P_8 |UNUSED | |8 | | | | | | | | | |
|
||||
|AA5 | | |VCCO_8 | | |8 | | | | |3.30 | | | | |
|
||||
|AA6 | | |GND | | | | | | | | | | | | |
|
||||
|AA7 | |IOBM |IO_L20P_8 |UNUSED | |8 | | | | | | | | | |
|
||||
|AA8 | |IOBM |IO_L26P_8 |UNUSED | |8 | | | | | | | | | |
|
||||
|AA9 | |IOBM |IO_L21P_8 |UNUSED | |8 | | | | | | | | | |
|
||||
|AA10 | |IOBS |IO_L27N_8 |UNUSED | |8 | | | | | | | | | |
|
||||
|AA11 | |LOWCAPIOB|IO_L6N_D4_LC_2 |UNUSED | |2 | | | | | | | | | |
|
||||
|AA12 | |LOWCAPIOB|IO_L6P_D5_LC_2 |UNUSED | |2 | | | | | | | | | |
|
||||
|AA13 | |LOWCAPIOB|IO_L4N_D8_VREF_LC_2 |UNUSED | |2 | | | | | | | | | |
|
||||
|AA14 | |LOWCAPIOB|IO_L1P_D15_CC_LC_2 |UNUSED | |2 | | | | | | | | | |
|
||||
|AA15 | |LOWCAPIOB|IO_L3N_D10_LC_2 |UNUSED | |2 | | | | | | | | | |
|
||||
|AA16 | |LOWCAPIOB|IO_L3P_D11_LC_2 |UNUSED | |2 | | | | | | | | | |
|
||||
|AA17 | |IOBS |IO_L27N_SM5_7 |UNUSED | |7 | | | | | | | | | |
|
||||
|AA18 | |IOBM |IO_L21P_7 |UNUSED | |7 | | | | | | | | | |
|
||||
|AA19 | |IOBM |IO_L26P_SM6_7 |UNUSED | |7 | | | | | | | | | |
|
||||
|AA20 | |IOBS |IO_L26N_SM6_7 |UNUSED | |7 | | | | | | | | | |
|
||||
|AA21 | | |GND | | | | | | | | | | | | |
|
||||
|AA22 | | |VCCO_7 | | |7 | | | | |any******| | | | |
|
||||
|AA23 | |IOBS |IO_L14N_7 |UNUSED | |7 | | | | | | | | | |
|
||||
|AA24 | |LOWCAPIOB|IO_L8P_CC_LC_7 |UNUSED | |7 | | | | | | | | | |
|
||||
|AA25 | | |VCCO_7 | | |7 | | | | |any******| | | | |
|
||||
|AA26 | |IOBS |IO_L10N_7 |UNUSED | |7 | | | | | | | | | |
|
||||
|AB1 | |IOBM |IO_L10P_8 |UNUSED | |8 | | | | | | | | | |
|
||||
|AB2 | |IOBS |IO_L12N_VREF_8 |UNUSED | |8 | | | | | | | | | |
|
||||
|AB3 | |IOBM |IO_L12P_8 |UNUSED | |8 | | | | | | | | | |
|
||||
|AB4 | |IOBS |IO_L11N_8 |UNUSED | |8 | | | | | | | | | |
|
||||
|AB5 | |IOBS |IO_L13N_8 |UNUSED | |8 | | | | | | | | | |
|
||||
|AB6 | |LOWCAPIOB|IO_L24N_CC_LC_8 |UNUSED | |8 | | | | | | | | | |
|
||||
|AB7 | |IOBS |IO_L28N_VREF_8 |UNUSED | |8 | | | | | | | | | |
|
||||
|AB8 | | |VCCO_8 | | |8 | | | | |3.30 | | | | |
|
||||
|AB9 | |IOBS |IO_L29N_8 |UNUSED | |8 | | | | | | | | | |
|
||||
|AB10 | |LOWCAPIOB|IO_L2N_GC_LC_4 |UNUSED | |4 | | | | | | | | | |
|
||||
|AB11 | | |VCCO_2 | | |2 | | | | |any******| | | | |
|
||||
|AB12 | | |GND | | | | | | | | | | | | |
|
||||
|AB13 | |LOWCAPIOB|IO_L4P_D9_LC_2 |UNUSED | |2 | | | | | | | | | |
|
||||
|AB14 | |LOWCAPIOB|IO_L1N_D14_CC_LC_2 |UNUSED | |2 | | | | | | | | | |
|
||||
|AB15 | | |GND | | | | | | | | | | | | |
|
||||
|AB16 | | |VCCO_2 | | |2 | | | | |any******| | | | |
|
||||
|AB17 | |LOWCAPIOB|IO_L3P_GC_LC_4 |UNUSED | |4 | | | | | | | | | |
|
||||
|AB18 | |IOBS |IO_L29N_SM4_7 |UNUSED | |7 | | | | | | | | | |
|
||||
|AB19 | | |VCCO_7 | | |7 | | | | |any******| | | | |
|
||||
|AB20 | |IOBM |IO_L28P_7 |UNUSED | |7 | | | | | | | | | |
|
||||
|AB21 | |LOWCAPIOB|IO_L24N_CC_LC_7 |UNUSED | |7 | | | | | | | | | |
|
||||
|AB22 | |IOBS |IO_L13N_7 |UNUSED | |7 | | | | | | | | | |
|
||||
|AB23 | |IOBM |IO_L14P_7 |UNUSED | |7 | | | | | | | | | |
|
||||
|AB24 | |IOBM |IO_L7P_7 |UNUSED | |7 | | | | | | | | | |
|
||||
|AB25 | |IOBS |IO_L7N_7 |UNUSED | |7 | | | | | | | | | |
|
||||
|AB26 | |IOBM |IO_L10P_7 |UNUSED | |7 | | | | | | | | | |
|
||||
|AC1 | |IOBS |IO_L14N_8 |UNUSED | |8 | | | | | | | | | |
|
||||
|AC2 | |IOBM |IO_L14P_8 |UNUSED | |8 | | | | | | | | | |
|
||||
|AC3 | |IOBS |IO_L18N_8 |UNUSED | |8 | | | | | | | | | |
|
||||
|AC4 | |IOBM |IO_L11P_8 |UNUSED | |8 | | | | | | | | | |
|
||||
|AC5 | |IOBM |IO_L13P_8 |UNUSED | |8 | | | | | | | | | |
|
||||
|AC6 | |LOWCAPIOB|IO_L24P_CC_LC_8 |UNUSED | |8 | | | | | | | | | |
|
||||
|AC7 | |IOBM |IO_L28P_8 |UNUSED | |8 | | | | | | | | | |
|
||||
|AC8 | |IOBS |IO_L32N_8 |UNUSED | |8 | | | | | | | | | |
|
||||
|AC9 | |IOBM |IO_L29P_8 |UNUSED | |8 | | | | | | | | | |
|
||||
|AC10 | |LOWCAPIOB|IO_L2P_GC_LC_4 |UNUSED | |4 | | | | | | | | | |
|
||||
|AC11 | |LOWCAPIOB|IO_L2N_D12_LC_2 |UNUSED | |2 | | | | | | | | | |
|
||||
|AC12 | |LOWCAPIOB|IO_L2P_D13_LC_2 |UNUSED | |2 | | | | | | | | | |
|
||||
|AC13 | |LOWCAPIOB|IO_L8P_D1_LC_2 |UNUSED | |2 | | | | | | | | | |
|
||||
|AC14 | |LOWCAPIOB|IO_L5P_D7_LC_2 |UNUSED | |2 | | | | | | | | | |
|
||||
|AC15 | |LOWCAPIOB|IO_L7N_D2_LC_2 |UNUSED | |2 | | | | | | | | | |
|
||||
|AC16 | |LOWCAPIOB|IO_L7P_D3_LC_2 |UNUSED | |2 | | | | | | | | | |
|
||||
|AC17 | |LOWCAPIOB|IO_L3N_GC_LC_4 |UNUSED | |4 | | | | | | | | | |
|
||||
|AC18 | |IOBM |IO_L29P_SM4_7 |UNUSED | |7 | | | | | | | | | |
|
||||
|AC19 | |LOWCAPIOB|IO_L25N_CC_SM7_LC_7 |UNUSED | |7 | | | | | | | | | |
|
||||
|AC20 | |IOBS |IO_L28N_VREF_7 |UNUSED | |7 | | | | | | | | | |
|
||||
|AC21 | |LOWCAPIOB|IO_L24P_CC_LC_7 |UNUSED | |7 | | | | | | | | | |
|
||||
|AC22 | |IOBM |IO_L13P_7 |UNUSED | |7 | | | | | | | | | |
|
||||
|AC23 | |IOBM |IO_L16P_7 |UNUSED | |7 | | | | | | | | | |
|
||||
|AC24 | |IOBS |IO_L16N_7 |UNUSED | |7 | | | | | | | | | |
|
||||
|AC25 | |LOWCAPIOB|IO_L9P_CC_LC_7 |UNUSED | |7 | | | | | | | | | |
|
||||
|AC26 | |LOWCAPIOB|IO_L9N_CC_LC_7 |UNUSED | |7 | | | | | | | | | |
|
||||
|AD1 | |IOBS |IO_L16N_8 |UNUSED | |8 | | | | | | | | | |
|
||||
|AD2 | |IOBM |IO_L16P_8 |UNUSED | |8 | | | | | | | | | |
|
||||
|AD3 | |IOBM |IO_L18P_8 |UNUSED | |8 | | | | | | | | | |
|
||||
|AD4 | |IOBS |IO_L22N_8 |UNUSED | |8 | | | | | | | | | |
|
||||
|AD5 | |IOBM |IO_L22P_8 |UNUSED | |8 | | | | | | | | | |
|
||||
|AD6 | |IOBS |IO_L30N_8 |UNUSED | |8 | | | | | | | | | |
|
||||
|AD7 | |IOBS |IO_L23N_VRP_8 |UNUSED | |8 | | | | | | | | | |
|
||||
|AD8 | |IOBM |IO_L32P_8 |UNUSED | |8 | | | | | | | | | |
|
||||
|AD9 | | |GND | | | | | | | | | | | | |
|
||||
|AD10 | |LOWCAPIOB|IO_L6N_GC_LC_4 |UNUSED | |4 | | | | | | | | | |
|
||||
|AD11 | |LOWCAPIOB|IO_L8N_GC_CC_LC_4 |UNUSED | |4 | | | | | | | | | |
|
||||
|AD12 | |LOWCAPIOB|IO_L8P_GC_CC_LC_4 |UNUSED | |4 | | | | | | | | | |
|
||||
|AD13 | |LOWCAPIOB|IO_L8N_D0_LC_2 |UNUSED | |2 | | | | | | | | | |
|
||||
|AD14 | |LOWCAPIOB|IO_L5N_D6_LC_2 |UNUSED | |2 | | | | | | | | | |
|
||||
|AD15 | | |VCCO_4 | | |4 | | | | |3.30 | | | | |
|
||||
|AD16 | |LOWCAPIOB|IO_L7N_GC_VRP_LC_4 |UNUSED | |4 | | | | | | | | | |
|
||||
|AD17 | |LOWCAPIOB|IO_L7P_GC_VRN_LC_4 |UNUSED | |4 | | | | | | | | | |
|
||||
|AD18 | | |GND | | | | | | | | | | | | |
|
||||
|AD19 | |LOWCAPIOB|IO_L25P_CC_SM7_LC_7 |UNUSED | |7 | | | | | | | | | |
|
||||
|AD20 | |IOBS |IO_L23N_VRP_7 |UNUSED | |7 | | | | | | | | | |
|
||||
|AD21 | |IOBS |IO_L32N_SM1_7 |UNUSED | |7 | | | | | | | | | |
|
||||
|AD22 | |IOBM |IO_L15P_7 |UNUSED | |7 | | | | | | | | | |
|
||||
|AD23 | |IOBS |IO_L15N_7 |UNUSED | |7 | | | | | | | | | |
|
||||
|AD24 | | |GND | | | | | | | | | | | | |
|
||||
|AD25 | |IOBM |IO_L11P_7 |UNUSED | |7 | | | | | | | | | |
|
||||
|AD26 | |IOBS |IO_L11N_7 |UNUSED | |7 | | | | | | | | | |
|
||||
|AE1 | | |GND | | | | | | | | | | | | |
|
||||
|AE2 | | |GND | | | | | | | | | | | | |
|
||||
|AE3 | |IOBS |IO_L15N_8 |UNUSED | |8 | | | | | | | | | |
|
||||
|AE4 | |IOBS |IO_L17N_8 |UNUSED | |8 | | | | | | | | | |
|
||||
|AE5 | | |VCCO_8 | | |8 | | | | |3.30 | | | | |
|
||||
|AE6 | |IOBM |IO_L30P_8 |UNUSED | |8 | | | | | | | | | |
|
||||
|AE7 | |IOBM |IO_L23P_VRN_8 |UNUSED | |8 | | | | | | | | | |
|
||||
|AE8 | | |VCCO_8 | | |8 | | | | |3.30 | | | | |
|
||||
|AE9 | |IOBS |IO_L31N_8 |UNUSED | |8 | | | | | | | | | |
|
||||
|AE10 | |LOWCAPIOB|IO_L6P_GC_LC_4 |UNUSED | |4 | | | | | | | | | |
|
||||
|AE11 | | |VCCO_4 | | |4 | | | | |3.30 | | | | |
|
||||
|AE12 | |LOWCAPIOB|IO_L1N_GC_LC_4 |UNUSED | |4 | | | | | | | | | |
|
||||
|AE13 | |LOWCAPIOB|IO_L5N_GC_LC_4 |UNUSED | |4 | | | | | | | | | |
|
||||
|AE14 |sys_clk_in |IOB |IO_L5P_GC_LC_4 |INPUT |LVCMOS33 |4 | | | |NONE | |LOCATED | |NO |NONE |
|
||||
|AE15 | | |VREFN_SM | | | | | | | | | | | | |
|
||||
|AE16 | | |VREFP_SM | | | | | | | | | | | | |
|
||||
|AE17 | | |AVSS_SM | | | | | | | | | | | | |
|
||||
|AE18 | |IOBS |IO_L31N_SM2_7 |UNUSED | |7 | | | | | | | | | |
|
||||
|AE19 | | |VCCO_7 | | |7 | | | | |any******| | | | |
|
||||
|AE20 | |IOBM |IO_L23P_VRN_7 |UNUSED | |7 | | | | | | | | | |
|
||||
|AE21 | |IOBM |IO_L32P_SM1_7 |UNUSED | |7 | | | | | | | | | |
|
||||
|AE22 | | |VCCO_7 | | |7 | | | | |any******| | | | |
|
||||
|AE23 | |IOBS |IO_L19N_7 |UNUSED | |7 | | | | | | | | | |
|
||||
|AE24 | |IOBS |IO_L22N_7 |UNUSED | |7 | | | | | | | | | |
|
||||
|AE25 | | |GND | | | | | | | | | | | | |
|
||||
|AE26 | | |GND | | | | | | | | | | | | |
|
||||
|AF2 | | |GND | | | | | | | | | | | | |
|
||||
|AF3 | |IOBM |IO_L15P_8 |UNUSED | |8 | | | | | | | | | |
|
||||
|AF4 | |IOBM |IO_L17P_8 |UNUSED | |8 | | | | | | | | | |
|
||||
|AF5 | |IOBS |IO_L19N_8 |UNUSED | |8 | | | | | | | | | |
|
||||
|AF6 | |IOBM |IO_L19P_8 |UNUSED | |8 | | | | | | | | | |
|
||||
|AF7 | |LOWCAPIOB|IO_L25N_CC_LC_8 |UNUSED | |8 | | | | | | | | | |
|
||||
|AF8 | |LOWCAPIOB|IO_L25P_CC_LC_8 |UNUSED | |8 | | | | | | | | | |
|
||||
|AF9 | |IOBM |IO_L31P_8 |UNUSED | |8 | | | | | | | | | |
|
||||
|AF10 | |LOWCAPIOB|IO_L4N_GC_VREF_LC_4 |UNUSED | |4 | | | | | | | | | |
|
||||
|AF11 | |LOWCAPIOB|IO_L4P_GC_LC_4 |UNUSED | |4 | | | | | | | | | |
|
||||
|AF12 | |LOWCAPIOB|IO_L1P_GC_LC_4 |UNUSED | |4 | | | | | | | | | |
|
||||
|AF13 | | |GND | | | | | | | | | | | | |
|
||||
|AF14 | | |GND | | | | | | | | | | | | |
|
||||
|AF15 | |IPAD |VN_SM |UNUSED | | | | | | | | | | | |
|
||||
|AF16 | |IPAD |VP_SM |UNUSED | | | | | | | | | | | |
|
||||
|AF17 | | |AVDD_SM | | | | | | | | | | | | |
|
||||
|AF18 | |IOBM |IO_L31P_SM2_7 |UNUSED | |7 | | | | | | | | | |
|
||||
|AF19 | |IOBM |IO_L17P_7 |UNUSED | |7 | | | | | | | | | |
|
||||
|AF20 | |IOBS |IO_L17N_7 |UNUSED | |7 | | | | | | | | | |
|
||||
|AF21 | |IOBM |IO_L30P_SM3_7 |UNUSED | |7 | | | | | | | | | |
|
||||
|AF22 | |IOBS |IO_L30N_SM3_7 |UNUSED | |7 | | | | | | | | | |
|
||||
|AF23 | |IOBM |IO_L19P_7 |UNUSED | |7 | | | | | | | | | |
|
||||
|AF24 | |IOBM |IO_L22P_7 |UNUSED | |7 | | | | | | | | | |
|
||||
|AF25 | | |GND | | | | | | | | | | | | |
|
||||
|B1 | | |GND | | | | | | | | | | | | |
|
||||
|B2 | | |GND | | | | | | | | | | | | |
|
||||
|B3 | |IOBS |IO_L14N_6 |UNUSED | |6 | | | | | | | | | |
|
||||
|B4 | |IOBS |IO_L15N_6 |UNUSED | |6 | | | | | | | | | |
|
||||
|B5 | | |VCCO_6 | | |6 | | | | |2.50 | | | | |
|
||||
|B6 | |LOWCAPIOB|IO_L8P_CC_LC_6 |UNUSED | |6 | | | | | | | | | |
|
||||
|B7 | |IOBM |IO_L11P_6 |UNUSED | |6 | | | | | | | | | |
|
||||
|B8 | | |VCCO_6 | | |6 | | | | |2.50 | | | | |
|
||||
|B9 | |IOBS |IO_L13N_6 |UNUSED | |6 | | | | | | | | | |
|
||||
|B10 | |LOWCAPIOB|IO_L6N_GC_LC_3 |UNUSED | |3 | | | | | | | | | |
|
||||
|B11 | | |VCCO_3 | | |3 | | | | |2.50 | | | | |
|
||||
|B12 | |LOWCAPIOB|IO_L4N_GC_VREF_LC_3 |UNUSED | |3 | | | | | | | | | |
|
||||
|B13 | |LOWCAPIOB|IO_L4P_GC_LC_3 |UNUSED | |3 | | | | | | | | | |
|
||||
|B14 |ps2_mouse_clk |IOB |IO_L1N_GC_CC_LC_3 |BIDIR |LVCMOS25 |3 |2 |SLOW |NONE** |IFD | |LOCATED | |YES |NONE |
|
||||
|B15 | |LOWCAPIOB|IO_L1P_GC_CC_LC_3 |UNUSED | |3 | | | | | | | | | |
|
||||
|B16 | | |VCCO_3 | | |3 | | | | |2.50 | | | | |
|
||||
|B17 | |LOWCAPIOB|IO_L7P_GC_LC_3 |UNUSED | |3 | | | | | | | | | |
|
||||
|B18 | |IOBM |IO_L3P_5 |UNUSED | |5 | | | | | | | | | |
|
||||
|B19 | | |VCCO_5 | | |5 | | | | |any******| | | | |
|
||||
|B20 | |IOBS |IO_L2N_5 |UNUSED | |5 | | | | | | | | | |
|
||||
|B21 | |IOBS |IO_L6N_5 |UNUSED | |5 | | | | | | | | | |
|
||||
|B22 | | |VCCO_5 | | |5 | | | | |any******| | | | |
|
||||
|B23 | |IOBS |IO_L10N_5 |UNUSED | |5 | | | | | | | | | |
|
||||
|B24 | |IOBM |IO_L10P_5 |UNUSED | |5 | | | | | | | | | |
|
||||
|B25 | | |GND | | | | | | | | | | | | |
|
||||
|B26 | | |GND | | | | | | | | | | | | |
|
||||
|C1 | |IOBS |IO_L20N_VREF_6 |UNUSED | |6 | | | | | | | | | |
|
||||
|C2 | |IOBM |IO_L20P_6 |UNUSED | |6 | | | | | | | | | |
|
||||
|C3 | | |GND | | | | | | | | | | | | |
|
||||
|C4 | |IOBM |IO_L16P_6 |UNUSED | |6 | | | | | | | | | |
|
||||
|C5 | |IOBM |IO_L12P_6 |UNUSED | |6 | | | | | | | | | |
|
||||
|C6 | |LOWCAPIOB|IO_L8N_CC_LC_6 |UNUSED | |6 | | | | | | | | | |
|
||||
|C7 | |IOBS |IO_L11N_6 |UNUSED | |6 | | | | | | | | | |
|
||||
|C8 | |IOBS |IO_L2N_6 |UNUSED | |6 | | | | | | | | | |
|
||||
|C9 | | |GND | | | | | | | | | | | | |
|
||||
|C10 | |IOBS |IO_L1N_6 |UNUSED | |6 | | | | | | | | | |
|
||||
|C11 | |LOWCAPIOB|IO_L6P_D21_LC_1 |UNUSED | |1 | | | | | | | | | |
|
||||
|C12 | |LOWCAPIOB|IO_L8N_GC_LC_3 |UNUSED | |3 | | | | | | | | | |
|
||||
|C13 | |LOWCAPIOB|IO_L8P_GC_LC_3 |UNUSED | |3 | | | | | | | | | |
|
||||
|C14 |ps2_mouse_data|IOB |IO_L3N_GC_LC_3 |BIDIR |LVCMOS25 |3 |2 |SLOW |NONE** |IFD | |LOCATED | |YES |NONE |
|
||||
|C15 | |LOWCAPIOB|IO_L3P_GC_LC_3 |UNUSED | |3 | | | | | | | | | |
|
||||
|C16 | |LOWCAPIOB|IO_L7N_D18_LC_1 |UNUSED | |1 | | | | | | | | | |
|
||||
|C17 | |IOBM |IO_L1P_5 |UNUSED | |5 | | | | | | | | | |
|
||||
|C18 | | |GND | | | | | | | | | | | | |
|
||||
|C19 | |IOBM |IO_L7P_5 |UNUSED | |5 | | | | | | | | | |
|
||||
|C20 | |IOBM |IO_L2P_5 |UNUSED | |5 | | | | | | | | | |
|
||||
|C21 | |IOBM |IO_L6P_5 |UNUSED | |5 | | | | | | | | | |
|
||||
|C22 | |IOBS |IO_L14N_5 |UNUSED | |5 | | | | | | | | | |
|
||||
|C23 | |IOBS |IO_L21N_5 |UNUSED | |5 | | | | | | | | | |
|
||||
|C24 | |IOBS |IO_L16N_5 |UNUSED | |5 | | | | | | | | | |
|
||||
|C25 | |IOBS |IO_L20N_VREF_5 |UNUSED | |5 | | | | | | | | | |
|
||||
|C26 | |IOBM |IO_L20P_5 |UNUSED | |5 | | | | | | | | | |
|
||||
|D1 | |LOWCAPIOB|IO_L25N_CC_LC_6 |UNUSED | |6 | | | | | | | | | |
|
||||
|D2 | |LOWCAPIOB|IO_L25P_CC_LC_6 |UNUSED | |6 | | | | | | | | | |
|
||||
|D3 | |IOBM |IO_L22P_6 |UNUSED | |6 | | | | | | | | | |
|
||||
|D4 | |IOBS |IO_L16N_6 |UNUSED | |6 | | | | | | | | | |
|
||||
|D5 | |IOBS |IO_L12N_VREF_6 |UNUSED | |6 | | | | | | | | | |
|
||||
|D6 |sys_rst_n_in |IOB |IO_L17N_6 |INPUT |LVCMOS25 |6 | | |PULLUP |NONE | |LOCATED | |NO |NONE |
|
||||
|D7 | |IOBS |IO_L4N_VREF_6 |UNUSED | |6 | | | | | | | | | |
|
||||
|D8 | |IOBM |IO_L4P_6 |UNUSED | |6 | | | | | | | | | |
|
||||
|D9 | |IOBM |IO_L2P_6 |UNUSED | |6 | | | | | | | | | |
|
||||
|D10 | |IOBM |IO_L1P_6 |UNUSED | |6 | | | | | | | | | |
|
||||
|D11 | |LOWCAPIOB|IO_L6N_D20_LC_1 |UNUSED | |1 | | | | | | | | | |
|
||||
|D12 | |LOWCAPIOB|IO_L8N_D16_CC_LC_1 |UNUSED | |1 | | | | | | | | | |
|
||||
|D13 | |LOWCAPIOB|IO_L4N_D24_VREF_LC_1|UNUSED | |1 | | | | | | | | | |
|
||||
|D14 | |LOWCAPIOB|IO_L4P_D25_LC_1 |UNUSED | |1 | | | | | | | | | |
|
||||
|D15 | |LOWCAPIOB|IO_L5P_D23_LC_1 |UNUSED | |1 | | | | | | | | | |
|
||||
|D16 | |LOWCAPIOB|IO_L7P_D19_LC_1 |UNUSED | |1 | | | | | | | | | |
|
||||
|D17 | |IOBS |IO_L1N_5 |UNUSED | |5 | | | | | | | | | |
|
||||
|D18 | |IOBS |IO_L7N_5 |UNUSED | |5 | | | | | | | | | |
|
||||
|D19 | |IOBS |IO_L4N_VREF_5 |UNUSED | |5 | | | | | | | | | |
|
||||
|D20 | |IOBM |IO_L4P_5 |UNUSED | |5 | | | | | | | | | |
|
||||
|D21 | |IOBS |IO_L12N_VREF_5 |UNUSED | |5 | | | | | | | | | |
|
||||
|D22 | |IOBM |IO_L14P_5 |UNUSED | |5 | | | | | | | | | |
|
||||
|D23 | |IOBM |IO_L21P_5 |UNUSED | |5 | | | | | | | | | |
|
||||
|D24 | |IOBM |IO_L16P_5 |UNUSED | |5 | | | | | | | | | |
|
||||
|D25 | |LOWCAPIOB|IO_L25N_CC_LC_5 |UNUSED | |5 | | | | | | | | | |
|
||||
|D26 | |LOWCAPIOB|IO_L25P_CC_LC_5 |UNUSED | |5 | | | | | | | | | |
|
||||
|E1 | |IOBM |IO_L26P_6 |UNUSED | |6 | | | | | | | | | |
|
||||
|E2 | |LOWCAPIOB|IO_L24N_CC_LC_6 |UNUSED | |6 | | | | | | | | | |
|
||||
|E3 | |LOWCAPIOB|IO_L24P_CC_LC_6 |UNUSED | |6 | | | | | | | | | |
|
||||
|E4 | |IOBS |IO_L22N_6 |UNUSED | |6 | | | | | | | | | |
|
||||
|E5 | |IOBS |IO_L18N_6 |UNUSED | |6 | | | | | | | | | |
|
||||
|E6 | |IOBM |IO_L18P_6 |UNUSED | |6 | | | | | | | | | |
|
||||
|E7 | |IOBM |IO_L17P_6 |UNUSED | |6 | | | | | | | | | |
|
||||
|E8 | | |VCCO_6 | | |6 | | | | |2.50 | | | | |
|
||||
|E9 | |IOBM |IO_L7P_6 |UNUSED | |6 | | | | | | | | | |
|
||||
|E10 | |IOBS |IO_L5N_6 |UNUSED | |6 | | | | | | | | | |
|
||||
|E11 | | |VCCO_1 | | |1 | | | | |any******| | | | |
|
||||
|E12 | | |GND | | | | | | | | | | | | |
|
||||
|E13 | |LOWCAPIOB|IO_L8P_D17_CC_LC_1 |UNUSED | |1 | | | | | | | | | |
|
||||
|E14 | |LOWCAPIOB|IO_L5N_D22_LC_1 |UNUSED | |1 | | | | | | | | | |
|
||||
|E15 | | |GND | | | | | | | | | | | | |
|
||||
|E16 | | |VCCO_1 | | |1 | | | | |any******| | | | |
|
||||
|E17 | |IOBM |IO_L5P_5 |UNUSED | |5 | | | | | | | | | |
|
||||
|E18 | |IOBS |IO_L11N_5 |UNUSED | |5 | | | | | | | | | |
|
||||
|E19 | | |VCCO_5 | | |5 | | | | |any******| | | | |
|
||||
|E20 | |IOBS |IO_L19N_5 |UNUSED | |5 | | | | | | | | | |
|
||||
|E21 | |IOBM |IO_L12P_5 |UNUSED | |5 | | | | | | | | | |
|
||||
|E22 | |IOBS |IO_L18N_5 |UNUSED | |5 | | | | | | | | | |
|
||||
|E23 | |IOBM |IO_L18P_5 |UNUSED | |5 | | | | | | | | | |
|
||||
|E24 | |IOBS |IO_L27N_5 |UNUSED | |5 | | | | | | | | | |
|
||||
|E25 | |IOBM |IO_L27P_5 |UNUSED | |5 | | | | | | | | | |
|
||||
|E26 | |IOBS |IO_L29N_5 |UNUSED | |5 | | | | | | | | | |
|
||||
|F1 | |IOBS |IO_L26N_6 |UNUSED | |6 | | | | | | | | | |
|
||||
|F2 | | |VCCO_6 | | |6 | | | | |2.50 | | | | |
|
||||
|F3 | |IOBS |IO_L27N_6 |UNUSED | |6 | | | | | | | | | |
|
||||
|F4 | |IOBM |IO_L27P_6 |UNUSED | |6 | | | | | | | | | |
|
||||
|F5 | | |VCCO_6 | | |6 | | | | |2.50 | | | | |
|
||||
|F6 | | |GND | | | | | | | | | | | | |
|
||||
|F7 | |IOBM |IO_L19P_6 |UNUSED | |6 | | | | | | | | | |
|
||||
|F8 | |IOBM |IO_L10P_6 |UNUSED | |6 | | | | | | | | | |
|
||||
|F9 | |IOBS |IO_L7N_6 |UNUSED | |6 | | | | | | | | | |
|
||||
|F10 | |IOBM |IO_L5P_6 |UNUSED | |6 | | | | | | | | | |
|
||||
|F11 | |LOWCAPIOB|IO_L2N_D28_LC_1 |UNUSED | |1 | | | | | | | | | |
|
||||
|F12 | |LOWCAPIOB|IO_L2P_D29_LC_1 |UNUSED | |1 | | | | | | | | | |
|
||||
|F13 | |LOWCAPIOB|IO_L1N_D30_LC_1 |UNUSED | |1 | | | | | | | | | |
|
||||
|F14 | |LOWCAPIOB|IO_L1P_D31_LC_1 |UNUSED | |1 | | | | | | | | | |
|
||||
|F15 | |LOWCAPIOB|IO_L3N_D26_LC_1 |UNUSED | |1 | | | | | | | | | |
|
||||
|F16 | |LOWCAPIOB|IO_L3P_D27_LC_1 |UNUSED | |1 | | | | | | | | | |
|
||||
|F17 | |IOBS |IO_L5N_5 |UNUSED | |5 | | | | | | | | | |
|
||||
|F18 | |IOBM |IO_L11P_5 |UNUSED | |5 | | | | | | | | | |
|
||||
|F19 | |IOBS |IO_L17N_5 |UNUSED | |5 | | | | | | | | | |
|
||||
|F20 | |IOBM |IO_L19P_5 |UNUSED | |5 | | | | | | | | | |
|
||||
|F21 | | |GND | | | | | | | | | | | | |
|
||||
|F22 | | |VCCO_5 | | |5 | | | | |any******| | | | |
|
||||
|F23 | |LOWCAPIOB|IO_L24N_CC_LC_5 |UNUSED | |5 | | | | | | | | | |
|
||||
|F24 | |LOWCAPIOB|IO_L24P_CC_LC_5 |UNUSED | |5 | | | | | | | | | |
|
||||
|F25 | | |VCCO_5 | | |5 | | | | |any******| | | | |
|
||||
|F26 | |IOBM |IO_L29P_5 |UNUSED | |5 | | | | | | | | | |
|
||||
|G1 | |IOBS |IO_L30N_6 |UNUSED | |6 | | | | | | | | | |
|
||||
|G2 | |IOBM |IO_L30P_6 |UNUSED | |6 | | | | | | | | | |
|
||||
|G3 | |IOBS |IO_L28N_VREF_6 |UNUSED | |6 | | | | | | | | | |
|
||||
|G4 | |IOBM |IO_L28P_6 |UNUSED | |6 | | | | | | | | | |
|
||||
|G5 |led<0> |IOB |IO_L23N_VRP_6 |OUTPUT |LVCMOS25 |6 |2 |SLOW |NONE** | | |LOCATED | |NO |NONE |
|
||||
|G6 |led<1> |IOB |IO_L23P_VRN_6 |OUTPUT |LVCMOS25 |6 |2 |SLOW |NONE** | | |LOCATED | |NO |NONE |
|
||||
|G7 | |IOBS |IO_L19N_6 |UNUSED | |6 | | | | | | | | | |
|
||||
|G8 | |IOBS |IO_L10N_6 |UNUSED | |6 | | | | | | | | | |
|
||||
|G9 | |LOWCAPIOB|IO_L9N_CC_LC_6 |UNUSED | |6 | | | | | | | | | |
|
||||
|G10 | |LOWCAPIOB|IO_L9P_CC_LC_6 |UNUSED | |6 | | | | | | | | | |
|
||||
|G11 | | |CS_B_0 | | | | | | | | | | | | |
|
||||
|G12 | | |D_IN_0 | | | | | | | | | | | | |
|
||||
|G13 | | |TDN_0 | | | | | | | | | | | | |
|
||||
|G14 | | |CCLK_0 | | | | | | | | | | | | |
|
||||
|G15 | | |INIT_0 | | | | | | | | | | | | |
|
||||
|G16 | | |HSWAPEN_0 | | | | | | | | | | | | |
|
||||
|G17 | |LOWCAPIOB|IO_L9N_CC_LC_5 |UNUSED | |5 | | | | | | | | | |
|
||||
|G18 | |LOWCAPIOB|IO_L9P_CC_LC_5 |UNUSED | |5 | | | | | | | | | |
|
||||
|G19 | |IOBM |IO_L17P_5 |UNUSED | |5 | | | | | | | | | |
|
||||
|G20 | |IOBS |IO_L22N_5 |UNUSED | |5 | | | | | | | | | |
|
||||
|G21 | |IOBS |IO_L23N_VRP_5 |UNUSED | |5 | | | | | | | | | |
|
||||
|G22 | |IOBM |IO_L23P_VRN_5 |UNUSED | |5 | | | | | | | | | |
|
||||
|G23 | |IOBS |IO_L28N_VREF_5 |UNUSED | |5 | | | | | | | | | |
|
||||
|G24 | |IOBM |IO_L28P_5 |UNUSED | |5 | | | | | | | | | |
|
||||
|G25 | |IOBS |IO_L31N_5 |UNUSED | |5 | | | | | | | | | |
|
||||
|G26 | |IOBM |IO_L31P_5 |UNUSED | |5 | | | | | | | | | |
|
||||
|H1 | |IOBS |IO_L32N_6 |UNUSED | |6 | | | | | | | | | |
|
||||
|H2 | |IOBM |IO_L32P_6 |UNUSED | |6 | | | | | | | | | |
|
||||
|H3 | |IOBS |IO_L31N_6 |UNUSED | |6 | | | | | | | | | |
|
||||
|H4 | |IOBM |IO_L31P_6 |UNUSED | |6 | | | | | | | | | |
|
||||
|H5 | |IOBS |IO_L29N_6 |UNUSED | |6 | | | | | | | | | |
|
||||
|H6 | |IOBM |IO_L29P_6 |UNUSED | |6 | | | | | | | | | |
|
||||
|H7 | |IOBS |IO_L21N_6 |UNUSED | |6 | | | | | | | | | |
|
||||
|H8 | |IOBM |IO_L21P_6 |UNUSED | |6 | | | | | | | | | |
|
||||
|H9 | | |VCCO_6 | | |6 | | | | |2.50 | | | | |
|
||||
|H10 | | |VCCO_6 | | |6 | | | | |2.50 | | | | |
|
||||
|H11 | | |VCCAUX | | | | | | | |2.5 | | | | |
|
||||
|H12 | | |RDWR_B_0 | | | | | | | | | | | | |
|
||||
|H13 | | |TDP_0 | | | | | | | | | | | | |
|
||||
|H14 | | |DONE_0 | | | | | | | | | | | | |
|
||||
|H15 | | |PROGRAM_B_0 | | | | | | | | | | | | |
|
||||
|H16 | | |VCCAUX | | | | | | | |2.5 | | | | |
|
||||
|H17 | | |VCCAUX | | | | | | | |2.5 | | | | |
|
||||
|H18 | | |VCCO_5 | | |5 | | | | |any******| | | | |
|
||||
|H19 | | |VCCO_5 | | |5 | | | | |any******| | | | |
|
||||
|H20 | |IOBM |IO_L22P_5 |UNUSED | |5 | | | | | | | | | |
|
||||
|H21 | |IOBS |IO_L26N_5 |UNUSED | |5 | | | | | | | | | |
|
||||
|H22 | |IOBM |IO_L26P_5 |UNUSED | |5 | | | | | | | | | |
|
||||
|H23 | |IOBS |IO_L30N_5 |UNUSED | |5 | | | | | | | | | |
|
||||
|H24 | |IOBM |IO_L30P_5 |UNUSED | |5 | | | | | | | | | |
|
||||
|H25 | |IOBS |IO_L32N_5 |UNUSED | |5 | | | | | | | | | |
|
||||
|H26 | |IOBM |IO_L32P_5 |UNUSED | |5 | | | | | | | | | |
|
||||
|J1 | |IOBS |IO_L4N_VREF_10 |UNUSED | |10 | | | | | | | | | |
|
||||
|J2 | |IOBM |IO_L4P_10 |UNUSED | |10 | | | | | | | | | |
|
||||
|J3 | | |GND | | | | | | | | | | | | |
|
||||
|J4 | |IOBS |IO_L2N_10 |UNUSED | |10 | | | | | | | | | |
|
||||
|J5 | |IOBM |IO_L2P_10 |UNUSED | |10 | | | | | | | | | |
|
||||
|J6 | |IOBS |IO_L1N_10 |UNUSED | |10 | | | | | | | | | |
|
||||
|J7 | |IOBM |IO_L1P_10 |UNUSED | |10 | | | | | | | | | |
|
||||
|J8 | | |VCCO_6 | | |6 | | | | |2.50 | | | | |
|
||||
|J10 | | |VCCINT | | | | | | | |1.2 | | | | |
|
||||
|J11 | | |VCCINT | | | | | | | |1.2 | | | | |
|
||||
|J12 | | |VCCAUX | | | | | | | |2.5 | | | | |
|
||||
|J13 | | |GND | | | | | | | | | | | | |
|
||||
|J14 | | |GND | | | | | | | | | | | | |
|
||||
|J15 | | |VCCO_0 | | |0 | | | | |any******| | | | |
|
||||
|J16 | | |VCCINT | | | | | | | |1.2 | | | | |
|
||||
|J17 | | |VCCINT | | | | | | | |1.2 | | | | |
|
||||
|J19 | | |VCCO_5 | | |5 | | | | |any******| | | | |
|
||||
|J20 | |IOBS |IO_L1N_9 |UNUSED | |9 | | | | | | | | | |
|
||||
|J21 | |IOBM |IO_L1P_9 |UNUSED | |9 | | | | | | | | | |
|
||||
|J22 | |IOBS |IO_L2N_9 |UNUSED | |9 | | | | | | | | | |
|
||||
|J23 | |IOBM |IO_L2P_9 |UNUSED | |9 | | | | | | | | | |
|
||||
|J24 | | |GND | | | | | | | | | | | | |
|
||||
|J25 | |IOBS |IO_L4N_VREF_9 |UNUSED | |9 | | | | | | | | | |
|
||||
|J26 | |IOBM |IO_L4P_9 |UNUSED | |9 | | | | | | | | | |
|
||||
|K1 | |IOBS |IO_L10N_10 |UNUSED | |10 | | | | | | | | | |
|
||||
|K2 | |IOBS |IO_L7N_10 |UNUSED | |10 | | | | | | | | | |
|
||||
|K3 | |IOBM |IO_L7P_10 |UNUSED | |10 | | | | | | | | | |
|
||||
|K4 | |IOBS |IO_L6N_10 |UNUSED | |10 | | | | | | | | | |
|
||||
|K5 | |IOBM |IO_L6P_10 |UNUSED | |10 | | | | | | | | | |
|
||||
|K6 | |IOBS |IO_L3N_10 |UNUSED | |10 | | | | | | | | | |
|
||||
|K7 | |IOBM |IO_L3P_10 |UNUSED | |10 | | | | | | | | | |
|
||||
|K8 | | |VCCO_10 | | |10 | | | | |any******| | | | |
|
||||
|K9 | | |VCCINT | | | | | | | |1.2 | | | | |
|
||||
|K10 | | |VCCINT | | | | | | | |1.2 | | | | |
|
||||
|K11 | | |GND | | | | | | | | | | | | |
|
||||
|K12 | | |GND | | | | | | | | | | | | |
|
||||
|K13 | | |GND | | | | | | | | | | | | |
|
||||
|K14 | | |GND | | | | | | | | | | | | |
|
||||
|K15 | | |GND | | | | | | | | | | | | |
|
||||
|K16 | | |GND | | | | | | | | | | | | |
|
||||
|K17 | | |VCCINT | | | | | | | |1.2 | | | | |
|
||||
|K18 | | |VCCINT | | | | | | | |1.2 | | | | |
|
||||
|K19 | | |VCCO_9 | | |9 | | | | |any******| | | | |
|
||||
|K20 | |IOBS |IO_L5N_9 |UNUSED | |9 | | | | | | | | | |
|
||||
|K21 | |IOBS |IO_L3N_9 |UNUSED | |9 | | | | | | | | | |
|
||||
|K22 | |IOBM |IO_L3P_9 |UNUSED | |9 | | | | | | | | | |
|
||||
|K23 | |IOBS |IO_L7N_9 |UNUSED | |9 | | | | | | | | | |
|
||||
|K24 | |IOBM |IO_L7P_9 |UNUSED | |9 | | | | | | | | | |
|
||||
|K25 | |LOWCAPIOB|IO_L8N_CC_LC_9 |UNUSED | |9 | | | | | | | | | |
|
||||
|K26 | |LOWCAPIOB|IO_L8P_CC_LC_9 |UNUSED | |9 | | | | | | | | | |
|
||||
|L1 | |IOBM |IO_L10P_10 |UNUSED | |10 | | | | | | | | | |
|
||||
|L2 | | |VCCO_10 | | |10 | | | | |any******| | | | |
|
||||
|L3 | |LOWCAPIOB|IO_L8N_CC_LC_10 |UNUSED | |10 | | | | | | | | | |
|
||||
|L4 | |LOWCAPIOB|IO_L8P_CC_LC_10 |UNUSED | |10 | | | | | | | | | |
|
||||
|L5 | | |VCCO_10 | | |10 | | | | |any******| | | | |
|
||||
|L6 | |IOBS |IO_L5N_10 |UNUSED | |10 | | | | | | | | | |
|
||||
|L7 | |IOBM |IO_L5P_10 |UNUSED | |10 | | | | | | | | | |
|
||||
|L8 | |LOWCAPIOB|IO_L9N_CC_LC_10 |UNUSED | |10 | | | | | | | | | |
|
||||
|L9 | | |VCCINT | | | | | | | |1.2 | | | | |
|
||||
|L10 | | |VCCINT | | | | | | | |1.2 | | | | |
|
||||
|L11 | | |VCCINT | | | | | | | |1.2 | | | | |
|
||||
|L12 | | |GND | | | | | | | | | | | | |
|
||||
|L13 | | |GND | | | | | | | | | | | | |
|
||||
|L14 | | |GND | | | | | | | | | | | | |
|
||||
|L15 | | |GND | | | | | | | | | | | | |
|
||||
|L16 | | |VCCINT | | | | | | | |1.2 | | | | |
|
||||
|L17 | | |VCCINT | | | | | | | |1.2 | | | | |
|
||||
|L18 | | |VCCINT | | | | | | | |1.2 | | | | |
|
||||
|L19 | |IOBM |IO_L5P_9 |UNUSED | |9 | | | | | | | | | |
|
||||
|L20 | |IOBS |IO_L6N_9 |UNUSED | |9 | | | | | | | | | |
|
||||
|L21 | |IOBM |IO_L6P_9 |UNUSED | |9 | | | | | | | | | |
|
||||
|L22 | | |VCCO_9 | | |9 | | | | |any******| | | | |
|
||||
|L23 | |IOBS |IO_L10N_9 |UNUSED | |9 | | | | | | | | | |
|
||||
|L24 | |IOBM |IO_L10P_9 |UNUSED | |9 | | | | | | | | | |
|
||||
|L25 | | |VCCO_9 | | |9 | | | | |any******| | | | |
|
||||
|L26 | |IOBM |IO_L12P_9 |UNUSED | |9 | | | | | | | | | |
|
||||
|M1 | |IOBS |IO_L11N_10 |UNUSED | |10 | | | | | | | | | |
|
||||
|M2 | |IOBM |IO_L11P_10 |UNUSED | |10 | | | | | | | | | |
|
||||
|M3 | |IOBS |IO_L12N_VREF_10 |UNUSED | |10 | | | | | | | | | |
|
||||
|M4 | |IOBM |IO_L12P_10 |UNUSED | |10 | | | | | | | | | |
|
||||
|M5 | |IOBS |IO_L13N_10 |UNUSED | |10 | | | | | | | | | |
|
||||
|M6 | |IOBM |IO_L13P_10 |UNUSED | |10 | | | | | | | | | |
|
||||
|M7 | |IOBS |IO_L17N_10 |UNUSED | |10 | | | | | | | | | |
|
||||
|M8 | |LOWCAPIOB|IO_L9P_CC_LC_10 |UNUSED | |10 | | | | | | | | | |
|
||||
|M9 | | |VCCAUX | | | | | | | |2.5 | | | | |
|
||||
|M10 | | |GND | | | | | | | | | | | | |
|
||||
|M11 | | |GND | | | | | | | | | | | | |
|
||||
|M12 | | |VCCINT | | | | | | | |1.2 | | | | |
|
||||
|M13 | | |GND | | | | | | | | | | | | |
|
||||
|M14 | | |GND | | | | | | | | | | | | |
|
||||
|M15 | | |VCCINT | | | | | | | |1.2 | | | | |
|
||||
|M16 | | |GND | | | | | | | | | | | | |
|
||||
|M17 | | |GND | | | | | | | | | | | | |
|
||||
|M18 | | |VCCO_9 | | |9 | | | | |any******| | | | |
|
||||
|M19 | |LOWCAPIOB|IO_L9P_CC_LC_9 |UNUSED | |9 | | | | | | | | | |
|
||||
|M20 | |IOBS |IO_L13N_9 |UNUSED | |9 | | | | | | | | | |
|
||||
|M21 | |IOBM |IO_L13P_9 |UNUSED | |9 | | | | | | | | | |
|
||||
|M22 | |IOBS |IO_L14N_9 |UNUSED | |9 | | | | | | | | | |
|
||||
|M23 | |IOBM |IO_L14P_9 |UNUSED | |9 | | | | | | | | | |
|
||||
|M24 | |IOBS |IO_L11N_9 |UNUSED | |9 | | | | | | | | | |
|
||||
|M25 | |IOBM |IO_L11P_9 |UNUSED | |9 | | | | | | | | | |
|
||||
|M26 | |IOBS |IO_L12N_VREF_9 |UNUSED | |9 | | | | | | | | | |
|
||||
|N1 | | |VCCO_10 | | |10 | | | | |any******| | | | |
|
||||
|N2 | |IOBS |IO_L14N_10 |UNUSED | |10 | | | | | | | | | |
|
||||
|N3 | |IOBM |IO_L14P_10 |UNUSED | |10 | | | | | | | | | |
|
||||
|N4 | |IOBS |IO_L15N_10 |UNUSED | |10 | | | | | | | | | |
|
||||
|N5 | |IOBM |IO_L15P_10 |UNUSED | |10 | | | | | | | | | |
|
||||
|N6 | | |GND | | | | | | | | | | | | |
|
||||
|N7 | |IOBM |IO_L17P_10 |UNUSED | |10 | | | | | | | | | |
|
||||
|N8 | |IOBS |IO_L19N_10 |UNUSED | |10 | | | | | | | | | |
|
||||
|N9 | | |VCCAUX | | | | | | | |2.5 | | | | |
|
||||
|N10 | | |GND | | | | | | | | | | | | |
|
||||
|N11 | | |GND | | | | | | | | | | | | |
|
||||
|N12 | | |GND | | | | | | | | | | | | |
|
||||
|N13 | | |GND | | | | | | | | | | | | |
|
||||
|N14 | | |GND | | | | | | | | | | | | |
|
||||
|N15 | | |GND | | | | | | | | | | | | |
|
||||
|N16 | | |GND | | | | | | | | | | | | |
|
||||
|N17 | | |GND | | | | | | | | | | | | |
|
||||
|N18 | | |VCCAUX | | | | | | | |2.5 | | | | |
|
||||
|N19 | |LOWCAPIOB|IO_L9N_CC_LC_9 |UNUSED | |9 | | | | | | | | | |
|
||||
|N20 | |IOBS |IO_L17N_9 |UNUSED | |9 | | | | | | | | | |
|
||||
|N21 | |IOBM |IO_L17P_9 |UNUSED | |9 | | | | | | | | | |
|
||||
|N22 | |IOBS |IO_L16N_9 |UNUSED | |9 | | | | | | | | | |
|
||||
|N23 | |IOBM |IO_L16P_9 |UNUSED | |9 | | | | | | | | | |
|
||||
|N24 | |IOBS |IO_L15N_9 |UNUSED | |9 | | | | | | | | | |
|
||||
|N25 | |IOBM |IO_L15P_9 |UNUSED | |9 | | | | | | | | | |
|
||||
|N26 | | |GND | | | | | | | | | | | | |
|
||||
|P1 | | |GND | | | | | | | | | | | | |
|
||||
|P2 | |IOBS |IO_L16N_10 |UNUSED | |10 | | | | | | | | | |
|
||||
|P3 | |IOBM |IO_L16P_10 |UNUSED | |10 | | | | | | | | | |
|
||||
|P4 | |IOBS |IO_L18N_10 |UNUSED | |10 | | | | | | | | | |
|
||||
|P5 | |IOBM |IO_L18P_10 |UNUSED | |10 | | | | | | | | | |
|
||||
|P6 | |IOBS |IO_L21N_10 |UNUSED | |10 | | | | | | | | | |
|
||||
|P7 | |IOBM |IO_L21P_10 |UNUSED | |10 | | | | | | | | | |
|
||||
|P8 | |IOBM |IO_L19P_10 |UNUSED | |10 | | | | | | | | | |
|
||||
|P9 | | |VCCAUX | | | | | | | |2.5 | | | | |
|
||||
|P10 | | |GND | | | | | | | | | | | | |
|
||||
|P11 | | |GND | | | | | | | | | | | | |
|
||||
|P12 | | |GND | | | | | | | | | | | | |
|
||||
|P13 | | |GND | | | | | | | | | | | | |
|
||||
|P14 | | |GND | | | | | | | | | | | | |
|
||||
|P15 | | |GND | | | | | | | | | | | | |
|
||||
|P16 | | |GND | | | | | | | | | | | | |
|
||||
|P17 | | |GND | | | | | | | | | | | | |
|
||||
|P18 | | |VCCAUX | | | | | | | |2.5 | | | | |
|
||||
|P19 | |IOBS |IO_L21N_9 |UNUSED | |9 | | | | | | | | | |
|
||||
|P20 | |IOBM |IO_L21P_9 |UNUSED | |9 | | | | | | | | | |
|
||||
|P21 | | |GND | | | | | | | | | | | | |
|
||||
|P22 | |IOBS |IO_L19N_9 |UNUSED | |9 | | | | | | | | | |
|
||||
|P23 | |IOBM |IO_L19P_9 |UNUSED | |9 | | | | | | | | | |
|
||||
|P24 | |IOBS |IO_L18N_9 |UNUSED | |9 | | | | | | | | | |
|
||||
|P25 | |IOBM |IO_L18P_9 |UNUSED | |9 | | | | | | | | | |
|
||||
|P26 | | |VCCO_9 | | |9 | | | | |any******| | | | |
|
||||
|R1 | |IOBS |IO_L22N_10 |UNUSED | |10 | | | | | | | | | |
|
||||
|R2 | |IOBM |IO_L22P_10 |UNUSED | |10 | | | | | | | | | |
|
||||
|R3 | |IOBS |IO_L20N_VREF_10 |UNUSED | |10 | | | | | | | | | |
|
||||
|R4 | |IOBM |IO_L20P_10 |UNUSED | |10 | | | | | | | | | |
|
||||
|R5 | |IOBS |IO_L23N_VRP_10 |UNUSED | |10 | | | | | | | | | |
|
||||
|R6 | |IOBM |IO_L23P_VRN_10 |UNUSED | |10 | | | | | | | | | |
|
||||
|R7 | |LOWCAPIOB|IO_L25N_CC_LC_10 |UNUSED | |10 | | | | | | | | | |
|
||||
|R8 | |LOWCAPIOB|IO_L25P_CC_LC_10 |UNUSED | |10 | | | | | | | | | |
|
||||
|R9 | | |VCCO_10 | | |10 | | | | |any******| | | | |
|
||||
|R10 | | |GND | | | | | | | | | | | | |
|
||||
|R11 | | |GND | | | | | | | | | | | | |
|
||||
|R12 | | |VCCINT | | | | | | | |1.2 | | | | |
|
||||
|R13 | | |GND | | | | | | | | | | | | |
|
||||
|R14 | | |GND | | | | | | | | | | | | |
|
||||
|R15 | | |VCCINT | | | | | | | |1.2 | | | | |
|
||||
|R16 | | |GND | | | | | | | | | | | | |
|
||||
|R17 | | |GND | | | | | | | | | | | | |
|
||||
|R18 | | |VCCAUX | | | | | | | |2.5 | | | | |
|
||||
|R19 | |LOWCAPIOB|IO_L25N_CC_LC_9 |UNUSED | |9 | | | | | | | | | |
|
||||
|R20 | |LOWCAPIOB|IO_L25P_CC_LC_9 |UNUSED | |9 | | | | | | | | | |
|
||||
|R21 | |IOBS |IO_L23N_VRP_9 |UNUSED | |9 | | | | | | | | | |
|
||||
|R22 | |IOBM |IO_L23P_VRN_9 |UNUSED | |9 | | | | | | | | | |
|
||||
|R23 | |IOBS |IO_L22N_9 |UNUSED | |9 | | | | | | | | | |
|
||||
|R24 | |IOBM |IO_L22P_9 |UNUSED | |9 | | | | | | | | | |
|
||||
|R25 | |IOBS |IO_L20N_VREF_9 |UNUSED | |9 | | | | | | | | | |
|
||||
|R26 | |IOBM |IO_L20P_9 |UNUSED | |9 | | | | | | | | | |
|
||||
|T1 | |LOWCAPIOB|IO_L24N_CC_LC_10 |UNUSED | |10 | | | | | | | | | |
|
||||
|T2 | | |VCCO_10 | | |10 | | | | |any******| | | | |
|
||||
|T3 | |IOBS |IO_L26N_10 |UNUSED | |10 | | | | | | | | | |
|
||||
|T4 | |IOBM |IO_L26P_10 |UNUSED | |10 | | | | | | | | | |
|
||||
|T5 | | |VCCO_10 | | |10 | | | | |any******| | | | |
|
||||
|T6 | |IOBS |IO_L27N_10 |UNUSED | |10 | | | | | | | | | |
|
||||
|T7 | |IOBM |IO_L27P_10 |UNUSED | |10 | | | | | | | | | |
|
||||
|T8 | |IOBM |IO_L31P_10 |UNUSED | |10 | | | | | | | | | |
|
||||
|T9 | | |VCCINT | | | | | | | |1.2 | | | | |
|
||||
|T10 | | |VCCINT | | | | | | | |1.2 | | | | |
|
||||
|T11 | | |VCCINT | | | | | | | |1.2 | | | | |
|
||||
|T12 | | |GND | | | | | | | | | | | | |
|
||||
|T13 | | |GND | | | | | | | | | | | | |
|
||||
|T14 | | |GND | | | | | | | | | | | | |
|
||||
|T15 | | |GND | | | | | | | | | | | | |
|
||||
|T16 | | |VCCINT | | | | | | | |1.2 | | | | |
|
||||
|T17 | | |VCCINT | | | | | | | |1.2 | | | | |
|
||||
|T18 | | |VCCINT | | | | | | | |1.2 | | | | |
|
||||
|T19 | |IOBS |IO_L31N_9 |UNUSED | |9 | | | | | | | | | |
|
||||
|T20 | |IOBS |IO_L30N_9 |UNUSED | |9 | | | | | | | | | |
|
||||
|T21 | |IOBM |IO_L30P_9 |UNUSED | |9 | | | | | | | | | |
|
||||
|T22 | | |VCCO_9 | | |9 | | | | |any******| | | | |
|
||||
|T23 | |LOWCAPIOB|IO_L24N_CC_LC_9 |UNUSED | |9 | | | | | | | | | |
|
||||
|T24 | |LOWCAPIOB|IO_L24P_CC_LC_9 |UNUSED | |9 | | | | | | | | | |
|
||||
|T25 | | |VCCO_9 | | |9 | | | | |any******| | | | |
|
||||
|T26 | |IOBM |IO_L26P_9 |UNUSED | |9 | | | | | | | | | |
|
||||
|U1 | |LOWCAPIOB|IO_L24P_CC_LC_10 |UNUSED | |10 | | | | | | | | | |
|
||||
|U2 | |IOBS |IO_L28N_VREF_10 |UNUSED | |10 | | | | | | | | | |
|
||||
|U3 | |IOBM |IO_L28P_10 |UNUSED | |10 | | | | | | | | | |
|
||||
|U4 | |IOBS |IO_L29N_10 |UNUSED | |10 | | | | | | | | | |
|
||||
|U5 | |IOBS |IO_L32N_10 |UNUSED | |10 | | | | | | | | | |
|
||||
|U6 | |IOBM |IO_L32P_10 |UNUSED | |10 | | | | | | | | | |
|
||||
|U7 | |IOBS |IO_L31N_10 |UNUSED | |10 | | | | | | | | | |
|
||||
|U8 | | |VCCO_10 | | |10 | | | | |any******| | | | |
|
||||
|U9 | | |VCCINT | | | | | | | |1.2 | | | | |
|
||||
|U10 | | |VCCINT | | | | | | | |1.2 | | | | |
|
||||
|U11 | | |GND | | | | | | | | | | | | |
|
||||
|U12 | | |GND | | | | | | | | | | | | |
|
||||
|U13 | | |GND | | | | | | | | | | | | |
|
||||
|U14 | | |GND | | | | | | | | | | | | |
|
||||
|U15 | | |GND | | | | | | | | | | | | |
|
||||
|U16 | | |GND | | | | | | | | | | | | |
|
||||
|U17 | | |VCCINT | | | | | | | |1.2 | | | | |
|
||||
|U18 | | |VCCINT | | | | | | | |1.2 | | | | |
|
||||
|U19 | | |VCCO_9 | | |9 | | | | |any******| | | | |
|
||||
|U20 | |IOBM |IO_L31P_9 |UNUSED | |9 | | | | | | | | | |
|
||||
|U21 | |IOBS |IO_L29N_9 |UNUSED | |9 | | | | | | | | | |
|
||||
|U22 | |IOBM |IO_L29P_9 |UNUSED | |9 | | | | | | | | | |
|
||||
|U23 | |IOBM |IO_L27P_9 |UNUSED | |9 | | | | | | | | | |
|
||||
|U24 | |IOBS |IO_L28N_VREF_9 |UNUSED | |9 | | | | | | | | | |
|
||||
|U25 | |IOBM |IO_L28P_9 |UNUSED | |9 | | | | | | | | | |
|
||||
|U26 | |IOBS |IO_L26N_9 |UNUSED | |9 | | | | | | | | | |
|
||||
|V1 | |IOBS |IO_L30N_10 |UNUSED | |10 | | | | | | | | | |
|
||||
|V2 | |IOBM |IO_L30P_10 |UNUSED | |10 | | | | | | | | | |
|
||||
|V3 | | |GND | | | | | | | | | | | | |
|
||||
|V4 | |IOBM |IO_L29P_10 |UNUSED | |10 | | | | | | | | | |
|
||||
|V5 | |IOBS |IO_L2N_8 |UNUSED | |8 | | | | | | | | | |
|
||||
|V6 | |IOBM |IO_L2P_8 |UNUSED | |8 | | | | | | | | | |
|
||||
|V7 | |IOBS |IO_L3N_8 |UNUSED | |8 | | | | | | | | | |
|
||||
|V8 | | |VCCO_8 | | |8 | | | | |3.30 | | | | |
|
||||
|V10 | | |VCCINT | | | | | | | |1.2 | | | | |
|
||||
|V11 | | |VCCINT | | | | | | | |1.2 | | | | |
|
||||
|V12 | | |VCCO_0 | | |0 | | | | |any******| | | | |
|
||||
|V13 | | |GND | | | | | | | | | | | | |
|
||||
|V14 | | |GND | | | | | | | | | | | | |
|
||||
|V15 | | |VCCAUX | | | | | | | |2.5 | | | | |
|
||||
|V16 | | |VCCINT | | | | | | | |1.2 | | | | |
|
||||
|V17 | | |VCCINT | | | | | | | |1.2 | | | | |
|
||||
|V19 | | |VCCO_7 | | |7 | | | | |any******| | | | |
|
||||
|V20 | |IOBS |IO_L5N_7 |UNUSED | |7 | | | | | | | | | |
|
||||
|V21 | |IOBM |IO_L1P_7 |UNUSED | |7 | | | | | | | | | |
|
||||
|V22 | |IOBS |IO_L1N_7 |UNUSED | |7 | | | | | | | | | |
|
||||
|V23 | |IOBS |IO_L27N_9 |UNUSED | |9 | | | | | | | | | |
|
||||
|V24 | | |GND | | | | | | | | | | | | |
|
||||
|V25 | |IOBS |IO_L32N_9 |UNUSED | |9 | | | | | | | | | |
|
||||
|V26 | |IOBM |IO_L32P_9 |UNUSED | |9 | | | | | | | | | |
|
||||
|W1 |sys_tx |IOB |IO_L1N_8 |OUTPUT |LVCMOS33 |8 |12 |SLOW |NONE** | | |LOCATED | |YES |NONE |
|
||||
|W2 |sys_rx |IOB |IO_L1P_8 |INPUT |LVCMOS33 |8 | | | |IFD | |LOCATED | |YES |NONE |
|
||||
|W3 | |IOBS |IO_L4N_VREF_8 |UNUSED | |8 | | | | | | | | | |
|
||||
|W4 | |IOBM |IO_L4P_8 |UNUSED | |8 | | | | | | | | | |
|
||||
|W5 | |IOBS |IO_L5N_8 |UNUSED | |8 | | | | | | | | | |
|
||||
|W6 | |IOBM |IO_L5P_8 |UNUSED | |8 | | | | | | | | | |
|
||||
|W7 | |IOBM |IO_L3P_8 |UNUSED | |8 | | | | | | | | | |
|
||||
|W8 | | |VCCO_8 | | |8 | | | | |3.30 | | | | |
|
||||
|W9 | | |VCCO_8 | | |8 | | | | |3.30 | | | | |
|
||||
|W10 | | |VCCAUX | | | | | | | |2.5 | | | | |
|
||||
|W11 | | |VCCAUX | | | | | | | |2.5 | | | | |
|
||||
|W12 | | |TCK_0 | | | | | | | | | | | | |
|
||||
|W13 | | |PWRDWN_B_0 | | | | | | | | | | | | |
|
||||
|W14 | | |M2_0 | | | | | | | | | | | | |
|
||||
|W15 | | |M0_0 | | | | | | | | | | | | |
|
||||
|W16 | | |VCCAUX | | | | | | | |2.5 | | | | |
|
||||
|W17 | | |VCCO_7 | | |7 | | | | |any******| | | | |
|
||||
|W18 | | |VCCO_7 | | |7 | | | | |any******| | | | |
|
||||
|W19 | |IOBS |IO_L18N_7 |UNUSED | |7 | | | | | | | | | |
|
||||
|W20 | |IOBM |IO_L5P_7 |UNUSED | |7 | | | | | | | | | |
|
||||
|W21 | |IOBM |IO_L3P_7 |UNUSED | |7 | | | | | | | | | |
|
||||
|W22 | |IOBS |IO_L3N_7 |UNUSED | |7 | | | | | | | | | |
|
||||
|W23 | |IOBM |IO_L4P_7 |UNUSED | |7 | | | | | | | | | |
|
||||
|W24 | |IOBS |IO_L4N_VREF_7 |UNUSED | |7 | | | | | | | | | |
|
||||
|W25 | |IOBM |IO_L2P_7 |UNUSED | |7 | | | | | | | | | |
|
||||
|W26 | |IOBS |IO_L2N_7 |UNUSED | |7 | | | | | | | | | |
|
||||
|Y1 | |IOBS |IO_L6N_8 |UNUSED | |8 | | | | | | | | | |
|
||||
|Y2 | |IOBM |IO_L6P_8 |UNUSED | |8 | | | | | | | | | |
|
||||
|Y3 | |LOWCAPIOB|IO_L8N_CC_LC_8 |UNUSED | |8 | | | | | | | | | |
|
||||
|Y4 | |LOWCAPIOB|IO_L8P_CC_LC_8 |UNUSED | |8 | | | | | | | | | |
|
||||
|Y5 | |LOWCAPIOB|IO_L9N_CC_LC_8 |UNUSED | |8 | | | | | | | | | |
|
||||
|Y6 | |LOWCAPIOB|IO_L9P_CC_LC_8 |UNUSED | |8 | | | | | | | | | |
|
||||
|Y7 | |IOBS |IO_L20N_VREF_8 |UNUSED | |8 | | | | | | | | | |
|
||||
|Y8 | |IOBS |IO_L26N_8 |UNUSED | |8 | | | | | | | | | |
|
||||
|Y9 | |IOBS |IO_L21N_8 |UNUSED | |8 | | | | | | | | | |
|
||||
|Y10 | |IOBM |IO_L27P_8 |UNUSED | |8 | | | | | | | | | |
|
||||
|Y11 | | |TMS_0 | | | | | | | | | | | | |
|
||||
|Y12 | | |TDI_0 | | | | | | | | | | | | |
|
||||
|Y13 | | |TDO_0 | | | | | | | | | | | | |
|
||||
|Y14 | | |DOUT_BUSY_0 | | | | | | | | | | | | |
|
||||
|Y15 | | |M1_0 | | | | | | | | | | | | |
|
||||
|Y16 | | |VBATT_0 | | | | | | | | | | | | |
|
||||
|Y17 | |IOBM |IO_L27P_SM5_7 |UNUSED | |7 | | | | | | | | | |
|
||||
|Y18 | |IOBS |IO_L21N_7 |UNUSED | |7 | | | | | | | | | |
|
||||
|Y19 | |IOBM |IO_L18P_7 |UNUSED | |7 | | | | | | | | | |
|
||||
|Y20 | |IOBM |IO_L20P_7 |UNUSED | |7 | | | | | | | | | |
|
||||
|Y21 | |IOBS |IO_L20N_VREF_7 |UNUSED | |7 | | | | | | | | | |
|
||||
|Y22 | |IOBM |IO_L12P_7 |UNUSED | |7 | | | | | | | | | |
|
||||
|Y23 | |IOBS |IO_L12N_VREF_7 |UNUSED | |7 | | | | | | | | | |
|
||||
|Y24 | |LOWCAPIOB|IO_L8N_CC_LC_7 |UNUSED | |7 | | | | | | | | | |
|
||||
|Y25 | |IOBM |IO_L6P_7 |UNUSED | |7 | | | | | | | | | |
|
||||
|Y26 | |IOBS |IO_L6N_7 |UNUSED | |7 | | | | | | | | | |
|
||||
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
|
||||
* Default value.
|
||||
** This default Pullup/Pulldown value can be overridden in Bitgen.
|
||||
****** Special VCCO requirements may apply. Please consult the device
|
||||
family datasheet for specific guideline on VCCO requirements.
|
||||
|
||||
|
||||
@@ -0,0 +1,57 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 18:09:51 10/22/05
|
||||
-- Design Name:
|
||||
-- Module Name: sipo - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Device:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
---- Uncomment the following library declaration if instantiating
|
||||
---- any Xilinx primitives in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity sipo is
|
||||
Generic (N : integer := 8);
|
||||
Port ( rst : in std_logic;
|
||||
clk : in std_logic;
|
||||
ce : in std_logic;
|
||||
d_in : in std_logic;
|
||||
d_out : out std_logic_vector(N-1 downto 0));
|
||||
end sipo;
|
||||
|
||||
architecture Behavioral of sipo is
|
||||
|
||||
signal reg : std_logic_vector(N-1 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
process (rst, clk, ce, d_in, reg)
|
||||
begin
|
||||
if rst ='1' then
|
||||
reg <= (others => '0');
|
||||
elsif clk'event and clk='1' then
|
||||
if ce = '1' then
|
||||
reg <= d_in & reg((N-1) downto 1);
|
||||
end if;
|
||||
end if;
|
||||
d_out <= reg;
|
||||
end process;
|
||||
|
||||
end Behavioral;
|
||||
@@ -0,0 +1,290 @@
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 20:35:49 10/22/2005
|
||||
-- Design Name: ps2_core
|
||||
-- Module Name: tb_ps2_core.vhd
|
||||
-- Project Name: ps2if
|
||||
-- Target Device:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- VHDL Test Bench Created by ISE for module: ps2_core
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
-- Notes:
|
||||
-- This testbench has been automatically generated using types std_logic and
|
||||
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
|
||||
-- that these types always be used for the top-level I/O of a design in order
|
||||
-- to guarantee that the testbench will bind correctly to the post-implementation
|
||||
-- simulation model.
|
||||
--------------------------------------------------------------------------------
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.std_logic_unsigned.all;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY tb_ps2_core_vhd IS
|
||||
END tb_ps2_core_vhd;
|
||||
|
||||
ARCHITECTURE behavior OF tb_ps2_core_vhd IS
|
||||
|
||||
-- Component Declaration for the Unit Under Test (UUT)
|
||||
COMPONENT ps2_core
|
||||
PORT(
|
||||
rst : IN std_logic;
|
||||
clk : IN std_logic;
|
||||
ce : IN std_logic;
|
||||
d_in : IN std_logic_vector(7 downto 0);
|
||||
write_en : IN std_logic;
|
||||
read_en : IN std_logic;
|
||||
ps2_clk_in : IN std_logic;
|
||||
ps2_data_in : IN std_logic;
|
||||
ps2_clk_out : out std_logic;
|
||||
ps2_data_out : out std_logic;
|
||||
d_out : OUT std_logic_vector(7 downto 0);
|
||||
input_rdy : OUT std_logic;
|
||||
output_rdy : OUT std_logic
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
--Constants
|
||||
constant SYSPERIOD : time := 10 ns;
|
||||
constant PS2PERIOD : time := 100 us;
|
||||
|
||||
--Inputs
|
||||
SIGNAL rst : std_logic := '1';
|
||||
SIGNAL clk : std_logic := '0';
|
||||
SIGNAL ce : std_logic := '1';
|
||||
SIGNAL write_en : std_logic := '0';
|
||||
SIGNAL read_en : std_logic := '0';
|
||||
SIGNAL ps2_clk_in : std_logic := '1';
|
||||
SIGNAL ps2_data_in : std_logic := '1';
|
||||
SIGNAL d_in : std_logic_vector(7 downto 0) := (others=>'0');
|
||||
|
||||
--Outputs
|
||||
SIGNAL d_out : std_logic_vector(7 downto 0);
|
||||
SIGNAL input_rdy : std_logic;
|
||||
SIGNAL output_rdy : std_logic;
|
||||
SIGNAL ps2_clk_i : std_logic := '1';
|
||||
SIGNAL ps2_clk_j : std_logic := '1';
|
||||
SIGNAL ps2_clk_out : std_logic;
|
||||
SIGNAL ps2_data_out : std_logic;
|
||||
SIGNAl tx_trig : std_logic := '0';
|
||||
|
||||
BEGIN
|
||||
|
||||
-- Instantiate the Unit Under Test (UUT)
|
||||
uut: ps2_core PORT MAP(
|
||||
rst => rst,
|
||||
clk => clk,
|
||||
ce => ce,
|
||||
d_in => d_in,
|
||||
d_out => d_out,
|
||||
input_rdy => input_rdy,
|
||||
output_rdy => output_rdy,
|
||||
write_en => write_en,
|
||||
read_en => read_en,
|
||||
ps2_clk_in => ps2_clk_in,
|
||||
ps2_data_in => ps2_data_in,
|
||||
ps2_clk_out => ps2_clk_out,
|
||||
ps2_data_out => ps2_data_out
|
||||
);
|
||||
|
||||
ps2_clk_j <= ps2_clk_i after PS2PERIOD/4;
|
||||
tb_pswclk : PROCESS
|
||||
BEGIN
|
||||
wait until ps2_clk_j'event;
|
||||
ps2_clk_in <= ps2_clk_j;
|
||||
|
||||
-- wait for SYSPERIOD;
|
||||
-- ps2_clk_in <= not ps2_clk_j;
|
||||
-- wait for SYSPERIOD;
|
||||
-- ps2_clk_in <= ps2_clk_j;
|
||||
-- wait for SYSPERIOD;
|
||||
-- ps2_clk_in <= not ps2_clk_j;
|
||||
-- wait for SYSPERIOD;
|
||||
-- ps2_clk_in <= ps2_clk_j;
|
||||
-- wait for SYSPERIOD;
|
||||
-- ps2_clk_in <= not ps2_clk_j;
|
||||
-- wait for SYSPERIOD;
|
||||
-- ps2_clk_in <= ps2_clk_j;
|
||||
-- wait for SYSPERIOD;
|
||||
-- ps2_clk_in <= not ps2_clk_j;
|
||||
-- wait for SYSPERIOD;
|
||||
-- ps2_clk_in <= ps2_clk_j;
|
||||
END PROCESS;
|
||||
|
||||
tb_sysclk : PROCESS
|
||||
BEGIN
|
||||
clk <= not clk;
|
||||
wait for SYSPERIOD/2;
|
||||
END PROCESS;
|
||||
|
||||
tb_read : PROCESS
|
||||
BEGIN
|
||||
if output_rdy = '1' then
|
||||
wait for 10*SYSPERIOD;
|
||||
read_en <= '1';
|
||||
end if;
|
||||
wait for 2*SYSPERIOD;
|
||||
read_en <= '0';
|
||||
|
||||
END PROCESS;
|
||||
|
||||
tb_write : PROCESS
|
||||
BEGIN
|
||||
wait until ps2_clk_out = '0';
|
||||
wait for PS2PERIOD;
|
||||
wait until ps2_data_out = '0';
|
||||
wait until ps2_clk_out = '1';
|
||||
wait for PS2PERIOD/2;
|
||||
tx_trig <= '1';
|
||||
|
||||
END PROCESS;
|
||||
|
||||
tb : PROCESS
|
||||
BEGIN
|
||||
|
||||
wait for 20*SYSPERIOD;
|
||||
rst <= '0';
|
||||
|
||||
for iter in 1 to 2 loop
|
||||
-- wait for 2*PS2PERIOD;
|
||||
|
||||
--Start bit
|
||||
wait for PS2PERIOD/2;
|
||||
ps2_clk_i <= '0';
|
||||
ps2_data_in <= '0';
|
||||
wait for PS2PERIOD/2;
|
||||
ps2_clk_i <= not ps2_clk_i;
|
||||
|
||||
--Data bit 0
|
||||
wait for PS2PERIOD/2;
|
||||
ps2_clk_i <= '0';
|
||||
ps2_data_in <= '1';
|
||||
wait for PS2PERIOD/2;
|
||||
ps2_clk_i <= not ps2_clk_i;
|
||||
|
||||
--Data bit 1
|
||||
wait for PS2PERIOD/2;
|
||||
ps2_clk_i <= '0';
|
||||
ps2_data_in <= '1';
|
||||
wait for PS2PERIOD/2;
|
||||
ps2_clk_i <= not ps2_clk_i;
|
||||
|
||||
--Data bit 2
|
||||
wait for PS2PERIOD/2;
|
||||
ps2_clk_i <= '0';
|
||||
ps2_data_in <= '0';
|
||||
wait for PS2PERIOD/2;
|
||||
ps2_clk_i <= not ps2_clk_i;
|
||||
|
||||
--Data bit 3
|
||||
wait for PS2PERIOD/2;
|
||||
ps2_clk_i <= '0';
|
||||
ps2_data_in <= '1';
|
||||
wait for PS2PERIOD/2;
|
||||
ps2_clk_i <= not ps2_clk_i;
|
||||
|
||||
--Data bit 4
|
||||
wait for PS2PERIOD/2;
|
||||
ps2_clk_i <= '0';
|
||||
ps2_data_in <= '1';
|
||||
wait for PS2PERIOD/2;
|
||||
ps2_clk_i <= not ps2_clk_i;
|
||||
|
||||
--Data bit 5
|
||||
wait for PS2PERIOD/2;
|
||||
ps2_clk_i <= '0';
|
||||
ps2_data_in <= '0';
|
||||
wait for PS2PERIOD/2;
|
||||
ps2_clk_i <= not ps2_clk_i;
|
||||
|
||||
--Data bit 6
|
||||
wait for PS2PERIOD/2;
|
||||
ps2_clk_i <= '0';
|
||||
ps2_data_in <= '1';
|
||||
wait for PS2PERIOD/2;
|
||||
ps2_clk_i <= not ps2_clk_i;
|
||||
|
||||
--Data bit 7
|
||||
wait for PS2PERIOD/2;
|
||||
ps2_clk_i <= '0';
|
||||
ps2_data_in <= '1';
|
||||
wait for PS2PERIOD/2;
|
||||
ps2_clk_i <= not ps2_clk_i;
|
||||
|
||||
--Parity
|
||||
wait for PS2PERIOD/2;
|
||||
ps2_clk_i <= '0';
|
||||
ps2_data_in <= '1';
|
||||
wait for PS2PERIOD/2;
|
||||
ps2_clk_i <= not ps2_clk_i;
|
||||
|
||||
--Stop
|
||||
wait for PS2PERIOD/2;
|
||||
ps2_clk_i <= '0';
|
||||
ps2_data_in <= '1';
|
||||
wait for PS2PERIOD/2;
|
||||
ps2_clk_i <= not ps2_clk_i;
|
||||
|
||||
end loop;
|
||||
|
||||
ps2_data_in <= '1';
|
||||
ps2_clk_i <= '1';
|
||||
|
||||
wait for PS2PERIOD;
|
||||
d_in <= x"A5";
|
||||
write_en <= '1';
|
||||
wait for SYSPERIOD;
|
||||
write_en <= '0';
|
||||
|
||||
wait until tx_trig = '1';
|
||||
wait for 2*PS2PERIOD;
|
||||
-- Start
|
||||
ps2_clk_i <= not ps2_clk_i;
|
||||
wait for PS2PERIOD/2;
|
||||
ps2_clk_i <= not ps2_clk_i;
|
||||
wait for PS2PERIOD/2;
|
||||
|
||||
for iter in 1 to 8 loop
|
||||
ps2_clk_i <= not ps2_clk_i;
|
||||
wait for PS2PERIOD/2;
|
||||
ps2_clk_i <= not ps2_clk_i;
|
||||
wait for PS2PERIOD/2;
|
||||
end loop;
|
||||
|
||||
-- Stop
|
||||
ps2_clk_i <= not ps2_clk_i;
|
||||
wait for PS2PERIOD/2;
|
||||
ps2_clk_i <= not ps2_clk_i;
|
||||
wait for PS2PERIOD/2;
|
||||
|
||||
-- Parity
|
||||
ps2_clk_i <= not ps2_clk_i;
|
||||
wait for PS2PERIOD/2;
|
||||
ps2_clk_i <= not ps2_clk_i;
|
||||
wait for PS2PERIOD/2;
|
||||
|
||||
ps2_data_in <= '0';
|
||||
ps2_clk_i <= not ps2_clk_i;
|
||||
wait for PS2PERIOD/2;
|
||||
|
||||
ps2_clk_i <= not ps2_clk_i;
|
||||
wait for PS2PERIOD/2;
|
||||
ps2_data_in <= '1';
|
||||
ps2_clk_i <= '1';
|
||||
-- Place stimulus here
|
||||
|
||||
wait; -- will wait forever
|
||||
END PROCESS;
|
||||
|
||||
END;
|
||||
@@ -0,0 +1,65 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 19:20:09 10/22/05
|
||||
-- Design Name:
|
||||
-- Module Name: timeout_counter - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Device:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
---- Uncomment the following library declaration if instantiating
|
||||
---- any Xilinx primitives in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity timeout_counter is
|
||||
Generic (N : integer := 8);
|
||||
Port ( rst : in std_logic;
|
||||
clk : in std_logic;
|
||||
ce : in std_logic;
|
||||
load : in integer range 0 to N-1;
|
||||
load_en : in std_logic;
|
||||
rdy : out std_logic);
|
||||
end timeout_counter;
|
||||
|
||||
architecture Behavioral of timeout_counter is
|
||||
signal count : integer range 0 to N-1;
|
||||
begin
|
||||
|
||||
process (rst, clk, ce, load, load_en)
|
||||
begin
|
||||
if rst='1' then
|
||||
count <= load;
|
||||
rdy <= '0';
|
||||
elsif clk='1' and clk'event then
|
||||
rdy <= '0';
|
||||
if load_en ='1' then
|
||||
count <= load;
|
||||
else
|
||||
if (count /= 0) then
|
||||
if ce ='1' then
|
||||
count <= count - 1;
|
||||
end if;
|
||||
else
|
||||
rdy <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end Behavioral;
|
||||
Reference in New Issue
Block a user