jens
5309734167
git-svn-id: http://moon:8086/svn/vhdl/trunk@1422 cc03376c-175c-47c8-b038-4cd826a8556b
61 lines
1.4 KiB
VHDL
61 lines
1.4 KiB
VHDL
--------------------------------------------------------------------------------
|
|
-- Company:
|
|
-- Engineer:
|
|
--
|
|
-- Create Date: 13:42:03 10/29/05
|
|
-- Design Name:
|
|
-- Module Name: piso - Behavioral
|
|
-- Project Name:
|
|
-- Target Device:
|
|
-- Tool versions:
|
|
-- Description:
|
|
--
|
|
-- Dependencies:
|
|
--
|
|
-- Revision:
|
|
-- Revision 0.01 - File Created
|
|
-- Additional Comments:
|
|
--
|
|
--------------------------------------------------------------------------------
|
|
library IEEE;
|
|
use IEEE.STD_LOGIC_1164.ALL;
|
|
use IEEE.STD_LOGIC_ARITH.ALL;
|
|
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
|
|
|
---- Uncomment the following library declaration if instantiating
|
|
---- any Xilinx primitives in this code.
|
|
--library UNISIM;
|
|
--use UNISIM.VComponents.all;
|
|
|
|
entity piso is
|
|
Generic (N : integer := 8);
|
|
Port ( rst : in std_logic;
|
|
clk : in std_logic;
|
|
ce : in std_logic;
|
|
load_en : in std_logic;
|
|
d_in : in std_logic_vector(N-1 downto 0);
|
|
d_out : out std_logic);
|
|
end piso;
|
|
|
|
architecture Behavioral of piso is
|
|
|
|
signal reg : std_logic_vector(N-1 downto 0);
|
|
|
|
begin
|
|
|
|
process (rst, clk, ce, reg, load_en, d_in)
|
|
begin
|
|
if rst ='1' then
|
|
reg <= (others => '0');
|
|
elsif load_en = '1' then
|
|
reg <= d_in;
|
|
elsif clk'event and clk='1' then
|
|
if ce = '1' then
|
|
reg <= '0' & reg((N-1) downto 1);
|
|
end if;
|
|
end if;
|
|
d_out <= reg(0);
|
|
end process;
|
|
|
|
end Behavioral;
|