- added
git-svn-id: http://moon:8086/svn/vhdl/trunk@1421 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
@@ -0,0 +1,63 @@
|
||||
# -------------------------------------------------
|
||||
# Global options
|
||||
# -------------------------------------------------
|
||||
LANG_STD := 93c
|
||||
IEEE_STD := standard
|
||||
WORK_PATH := work
|
||||
SOURCE_PATH := ../src
|
||||
LIB_PATH := ../../../lib
|
||||
|
||||
# -------------------------------------------------
|
||||
# Target options
|
||||
# -------------------------------------------------
|
||||
TARGET := tb_fir_parallel
|
||||
|
||||
SOURCES := ../../../lib/src/PCK_FIO-2002.7/PCK_FIO_1993.vhd \
|
||||
../../../lib/src/PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd \
|
||||
../../../lib/src/fixed_ja/fixed_ja.vhd \
|
||||
../../../lib/src/fixed_ja/fixed_ja_body.vhd \
|
||||
../src/filter_pkg.vhd \
|
||||
../src/fir_stage_pkg.vhd \
|
||||
../src/fir_stage.vhd \
|
||||
../src/fir_parallel_pkg.vhd \
|
||||
../src/fir_parallel.vhd \
|
||||
../src/tb_fir_parallel.vhd
|
||||
|
||||
# -------------------------------------------------
|
||||
GHDL_OPT := --workdir=$(WORK_PATH) --std=$(LANG_STD) --ieee=$(IEEE_STD)
|
||||
|
||||
# -------------------------------------------------
|
||||
all: elaborate
|
||||
|
||||
.PHONY: syntax
|
||||
syntax:
|
||||
ghdl -s $(GHDL_OPT) $(SOURCES)
|
||||
|
||||
import:
|
||||
ghdl -i $(GHDL_OPT) $(SOURCES)
|
||||
|
||||
analyze:
|
||||
ghdl -a $(GHDL_OPT) $(SOURCES)
|
||||
|
||||
anaborate:
|
||||
ghdl -c $(GHDL_OPT) $(SOURCES) -e $(TARGET)
|
||||
|
||||
makeunit: analyze
|
||||
ghdl -m $(GHDL_OPT) $(TARGET)
|
||||
|
||||
elaborate: analyze
|
||||
ghdl -e $(GHDL_OPT) $(TARGET)
|
||||
|
||||
run: elaborate
|
||||
ghdl -r $(GHDL_OPT) $(TARGET) --vcd=$(TARGET).vcd --assert-level=error
|
||||
|
||||
show: $(TARGET).vcd
|
||||
gtkwave $(TARGET).vcd $(TARGET).sav
|
||||
|
||||
# -------------------------------------------------
|
||||
.PHONY: clean
|
||||
clean:
|
||||
rm -rf $(TARGET)
|
||||
cd $(WORK_PATH); rm -rf *.o *.cf
|
||||
|
||||
# -------------------------------------------------
|
||||
@@ -0,0 +1,62 @@
|
||||
# -------------------------------------------------
|
||||
# Global options
|
||||
# -------------------------------------------------
|
||||
LANG_STD := 93c
|
||||
IEEE_STD := standard
|
||||
WORK_PATH := work
|
||||
SOURCE_PATH := ../src
|
||||
LIB_PATH := ../../../lib
|
||||
|
||||
# -------------------------------------------------
|
||||
# Target options
|
||||
# -------------------------------------------------
|
||||
TARGET := tb_nco
|
||||
|
||||
SOURCES := ../../../lib/src/PCK_FIO-2002.7/PCK_FIO_1993.vhd \
|
||||
../../../lib/src/PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd \
|
||||
../../../lib/src/fixed_ja/fixed_ja.vhd \
|
||||
../../../lib/src/fixed_ja/fixed_ja_body.vhd \
|
||||
../src/nco_pkg.vhd \
|
||||
../src/wavelut.vhd \
|
||||
../src/nco.vhd \
|
||||
../src/tb_nco.vhd
|
||||
|
||||
|
||||
# -------------------------------------------------
|
||||
GHDL_OPT := --workdir=$(WORK_PATH) --std=$(LANG_STD) --ieee=$(IEEE_STD)
|
||||
|
||||
# -------------------------------------------------
|
||||
all: elaborate
|
||||
|
||||
.PHONY: syntax
|
||||
syntax:
|
||||
ghdl -s $(GHDL_OPT) $(SOURCES)
|
||||
|
||||
import:
|
||||
ghdl -i $(GHDL_OPT) $(SOURCES)
|
||||
|
||||
analyze:
|
||||
ghdl -a $(GHDL_OPT) $(SOURCES)
|
||||
|
||||
anaborate:
|
||||
ghdl -c $(GHDL_OPT) $(SOURCES) -e $(TARGET)
|
||||
|
||||
makeunit: analyze
|
||||
ghdl -m $(GHDL_OPT) $(TARGET)
|
||||
|
||||
elaborate: analyze
|
||||
ghdl -e $(GHDL_OPT) $(TARGET)
|
||||
|
||||
run: elaborate
|
||||
ghdl -r $(GHDL_OPT) $(TARGET) --vcd=$(TARGET).vcd --assert-level=error
|
||||
|
||||
show: $(TARGET).vcd
|
||||
gtkwave $(TARGET).vcd $(TARGET).sav
|
||||
|
||||
# -------------------------------------------------
|
||||
.PHONY: clean
|
||||
clean:
|
||||
rm -rf $(TARGET)
|
||||
cd $(WORK_PATH); rm -rf *.o *.cf
|
||||
|
||||
# -------------------------------------------------
|
||||
@@ -0,0 +1,175 @@
|
||||
0.000000e+000
|
||||
0.000000e+000
|
||||
0.000000e+000
|
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0.000000e+000
|
||||
0.000000e+000
|
||||
0.000000e+000
|
||||
0.000000e+000
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||||
0.000000e+000
|
||||
0.000000e+000
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||||
0.000000e+000
|
||||
0.000000e+000
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0.000000e+000
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0.000000e+000
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0.000000e+000
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0.000000e+000
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0.000000e+000
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0.000000e+000
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0.000000e+000
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0.000000e+000
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0.000000e+000
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0.000000e+000
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0.000000e+000
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||||
-5.764961e-004
|
||||
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|
||||
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|
||||
0.000000e+000
|
||||
1.818752e-002
|
||||
3.929949e-002
|
||||
4.025936e-002
|
||||
0.000000e+000
|
||||
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|
||||
-1.467075e-001
|
||||
-1.400504e-001
|
||||
0.000000e+000
|
||||
2.748170e-001
|
||||
6.123896e-001
|
||||
8.916664e-001
|
||||
1.000000e+000
|
||||
8.916664e-001
|
||||
6.123896e-001
|
||||
2.748170e-001
|
||||
0.000000e+000
|
||||
-1.400504e-001
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||||
-1.467075e-001
|
||||
-7.685423e-002
|
||||
0.000000e+000
|
||||
4.025936e-002
|
||||
3.929949e-002
|
||||
1.818752e-002
|
||||
0.000000e+000
|
||||
-5.835533e-003
|
||||
-3.461361e-003
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||||
-5.764961e-004
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||||
0.000000e+000
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0.000000e+000
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0.000000e+000
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0.000000e+000
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0.000000e+000
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||||
0.000000e+000
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0.000000e+000
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0.000000e+000
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||||
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||||
0.000000e+000
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||||
0.000000e+000
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0.000000e+000
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||||
0.000000e+000
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0.000000e+000
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||||
0.000000e+000
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||||
0.000000e+000
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||||
0.000000e+000
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||||
0.000000e+000
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||||
0.000000e+000
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||||
0.000000e+000
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||||
0.000000e+000
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||||
0.000000e+000
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||||
0.000000e+000
|
||||
0.000000e+000
|
||||
0.000000e+000
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||||
0.000000e+000
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0.000000e+000
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||||
0.000000e+000
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||||
0.000000e+000
|
||||
0.000000e+000
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||||
0.000000e+000
|
||||
0.000000e+000
|
||||
0.000000e+000
|
||||
0.000000e+000
|
||||
0.000000e+000
|
||||
0.000000e+000
|
||||
0.000000e+000
|
||||
0.000000e+000
|
||||
0.000000e+000
|
||||
0.000000e+000
|
||||
0.000000e+000
|
||||
0.000000e+000
|
||||
0.000000e+000
|
||||
0.000000e+000
|
||||
0.000000e+000
|
||||
0.000000e+000
|
||||
0.000000e+000
|
||||
0.000000e+000
|
||||
0.000000e+000
|
||||
0.000000e+000
|
||||
0.000000e+000
|
||||
0.000000e+000
|
||||
0.000000e+000
|
||||
0.000000e+000
|
||||
0.000000e+000
|
||||
0.000000e+000
|
||||
0.000000e+000
|
||||
0.000000e+000
|
||||
0.000000e+000
|
||||
0.000000e+000
|
||||
0.000000e+000
|
||||
0.000000e+000
|
||||
0.000000e+000
|
||||
0.000000e+000
|
||||
0.000000e+000
|
||||
0.000000e+000
|
||||
0.000000e+000
|
||||
0.000000e+000
|
||||
0.000000e+000
|
||||
0.000000e+000
|
||||
0.000000e+000
|
||||
0.000000e+000
|
||||
0.000000e+000
|
||||
0.000000e+000
|
||||
0.000000e+000
|
||||
0.000000e+000
|
||||
0.000000e+000
|
||||
0.000000e+000
|
||||
0.000000e+000
|
||||
0.000000e+000
|
||||
0.000000e+000
|
||||
0.000000e+000
|
||||
0.000000e+000
|
||||
0.000000e+000
|
||||
0.000000e+000
|
||||
0.000000e+000
|
||||
0.000000e+000
|
||||
0.000000e+000
|
||||
0.000000e+000
|
||||
0.000000e+000
|
||||
0.000000e+000
|
||||
0.000000e+000
|
||||
@@ -0,0 +1,33 @@
|
||||
0.70107
|
||||
9.775391e-001
|
||||
6.577148e-001
|
||||
7.666016e-002
|
||||
-5.336914e-001
|
||||
-9.340820e-001
|
||||
-9.624023e-001
|
||||
-6.079102e-001
|
||||
-1.220703e-002
|
||||
5.869141e-001
|
||||
9.545898e-001
|
||||
9.433594e-001
|
||||
5.566406e-001
|
||||
-5.078125e-002
|
||||
-6.357422e-001
|
||||
-9.716797e-001
|
||||
-9.204102e-001
|
||||
-5.063477e-001
|
||||
1.118164e-001
|
||||
6.840820e-001
|
||||
9.843750e-001
|
||||
8.945313e-001
|
||||
4.482422e-001
|
||||
-1.738281e-001
|
||||
-7.285156e-001
|
||||
-9.931641e-001
|
||||
-8.637695e-001
|
||||
-3.925781e-001
|
||||
2.353516e-001
|
||||
7.700195e-001
|
||||
9.985352e-001
|
||||
8.315430e-001
|
||||
3.339844e-001
|
||||
Binary file not shown.
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,8 @@
|
||||
function in2wav(name)
|
||||
|
||||
fid = fopen(name, 'r');
|
||||
x = fread(fid, 'int');
|
||||
fclose(fid);
|
||||
|
||||
wavwrite(x*(2^-15), 44100, 'wav_out.wav');
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
Binary file not shown.
@@ -0,0 +1,61 @@
|
||||
% Read data
|
||||
function tb_result()
|
||||
fa = 100.0;
|
||||
f = 10.2;
|
||||
|
||||
I_ud = TEXTREAD('i_ud.txt')';
|
||||
I_d = TEXTREAD('i_d.txt')';
|
||||
LFSR = TEXTREAD('lfsr.txt');
|
||||
|
||||
N= length(I_ud);
|
||||
N_fft = min(16384, N);
|
||||
N_fft2 = N_fft/2;
|
||||
|
||||
fft_y2 = 2/N_fft*abs(fft(I_ud(1:N_fft).*hann(N_fft)'));
|
||||
fft_y3 = 2/N_fft*abs(fft(I_d(1:N_fft).*hann(N_fft)'));
|
||||
|
||||
[i, v] = get_maxpur(fft_y2, fa, f);
|
||||
max_spur_freq = (i*fa/N_fft);
|
||||
max_spur_value = 20*log10(v);
|
||||
|
||||
[i, v] = get_maxpur(fft_y3, fa, f);
|
||||
max_ditherd_spur_freq = (i*fa/N_fft);
|
||||
max_ditherd_spur_value = 20*log10(v);
|
||||
|
||||
% Output
|
||||
close all;
|
||||
|
||||
subplot(2,1,1)
|
||||
plot(fa/N_fft*(0:N_fft2),20*log10(1E-6+fft_y2(1:N_fft2+1)), '-', fa/N_fft*(0:N_fft2), max_spur_value*ones(1,N_fft2+1), 'r-', [max_spur_freq], [max_spur_value], 'ro'); grid;
|
||||
spur_legend = sprintf('Max. spur %.1fdB at %.1fMHz', max_spur_value, max_spur_freq);
|
||||
legend('With dithering', spur_legend);
|
||||
legend('No dithering', spur_legend);
|
||||
title('Table');
|
||||
ylabel('dB');
|
||||
xlabel('f/MHz');
|
||||
axis([0 fa/2 -120 0]);
|
||||
subplot(2,1,2)
|
||||
plot(fa/N_fft*(0:N_fft2),20*log10(1E-6+fft_y3(1:N_fft2+1)), '-', fa/N_fft*(0:N_fft2), max_ditherd_spur_value*ones(1,N_fft2+1), 'r-', [max_ditherd_spur_freq], [max_ditherd_spur_value], 'ro'); grid;
|
||||
spur_legend = sprintf('Max. spur %.1fdB at %.1fMHz', max_ditherd_spur_value, max_ditherd_spur_freq);
|
||||
legend('With dithering', spur_legend);
|
||||
title('Table');
|
||||
ylabel('dB');
|
||||
xlabel('f/MHz');
|
||||
axis([0 fa/2 -120 0]);
|
||||
|
||||
figure;
|
||||
hist(LFSR)
|
||||
|
||||
function [max_i, max_v] = get_maxpur(spec, fa, f)
|
||||
max_v = 0;
|
||||
max_i = 0;
|
||||
for ii=1:fix(length(spec)/2+1),
|
||||
fi = ii*fa/length(spec);
|
||||
dfi = fi - f;
|
||||
if abs(dfi) > 0.5
|
||||
if spec(ii) > max_v
|
||||
max_v = spec(ii);
|
||||
max_i = ii;
|
||||
end
|
||||
end;
|
||||
end;
|
||||
@@ -0,0 +1,15 @@
|
||||
## NOTE: Do not edit this file.
|
||||
## Autogenerated by ProjNav (creatfdo.tcl) on Sat Jun 02 11:22:21 Westeuropäische Sommerzeit 2007
|
||||
##
|
||||
vlib work
|
||||
vcom -explicit -93 "../../../lib/fixed/fixed_pkg_c.vhd"
|
||||
vcom -explicit -93 "../src/mix_cpx_pkg.vhd"
|
||||
vcom -explicit -93 "../src/mix_cpx.vhd"
|
||||
vcom -explicit -93 "../src/syn_mix_cpx.vhd"
|
||||
vcom -explicit -93 "../src/tb_syn_mix_cpx.vhd"
|
||||
vsim -t 1ps -lib work tb_syn_mix_cpx
|
||||
do {tb_syn_mix_cpx.wdo}
|
||||
view wave
|
||||
view structure
|
||||
view signals
|
||||
run 1000ns
|
||||
@@ -0,0 +1,14 @@
|
||||
## NOTE: Do not edit this file.
|
||||
## Auto generated by Project Navigator for Post-Translate Simulation
|
||||
##
|
||||
vlib work
|
||||
## Compile Post-Translate Model
|
||||
vcom -explicit -93 "../syn/mix_cpx/netgen/synthesis/syn_mix_cpx_synthesis.vhd"
|
||||
vcom -explicit -93 "../src/tb_syn_mix_cpx.vhd"
|
||||
vsim -t 1ps -lib work tb_syn_mix_cpx
|
||||
do {tb_syn_mix_cpx.wdo}
|
||||
view wave
|
||||
view structure
|
||||
view signals
|
||||
run 1000ns
|
||||
## End
|
||||
@@ -0,0 +1,34 @@
|
||||
onerror {resume}
|
||||
quietly WaveActivateNextPane {} 0
|
||||
add wave -noupdate -format Logic /tb_syn_mix_cpx/clk
|
||||
add wave -noupdate -format Logic /tb_syn_mix_cpx/srst
|
||||
add wave -noupdate -format Logic /tb_syn_mix_cpx/in_valid
|
||||
add wave -noupdate -format Literal /tb_syn_mix_cpx/x_re_in
|
||||
add wave -noupdate -format Literal /tb_syn_mix_cpx/x_im_in
|
||||
add wave -noupdate -format Literal /tb_syn_mix_cpx/y_re_in
|
||||
add wave -noupdate -format Literal /tb_syn_mix_cpx/y_im_in
|
||||
add wave -noupdate -format Literal /tb_syn_mix_cpx/z_re_out
|
||||
add wave -noupdate -format Literal /tb_syn_mix_cpx/z_im_out
|
||||
add wave -noupdate -format Logic /tb_syn_mix_cpx/out_valid
|
||||
add wave -noupdate -format Literal /tb_syn_mix_cpx/x_re
|
||||
add wave -noupdate -format Literal /tb_syn_mix_cpx/x_im
|
||||
add wave -noupdate -format Literal /tb_syn_mix_cpx/y_re
|
||||
add wave -noupdate -format Literal /tb_syn_mix_cpx/y_im
|
||||
add wave -noupdate -format Literal /tb_syn_mix_cpx/z_re
|
||||
add wave -noupdate -format Literal /tb_syn_mix_cpx/z_im
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 1} {0 ps} 0}
|
||||
configure wave -namecolwidth 150
|
||||
configure wave -valuecolwidth 100
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 1
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
configure wave -gridoffset 0
|
||||
configure wave -gridperiod 100
|
||||
configure wave -griddelta 40
|
||||
configure wave -timeline 1
|
||||
update
|
||||
WaveRestoreZoom {0 ps} {1 ns}
|
||||
@@ -0,0 +1,14 @@
|
||||
## NOTE: Do not edit this file.
|
||||
## Auto generated by Project Navigator for Post-Translate Simulation
|
||||
##
|
||||
vlib work
|
||||
## Compile Post-Translate Model
|
||||
vcom -explicit -93 "../syn/nco/netgen/synthesis/syn_nco_synthesis.vhd"
|
||||
vcom -explicit -93 "../src/tb_syn_nco.vhd"
|
||||
vsim -t 1ps -lib work tb_syn_nco
|
||||
do {tb_syn_nco.wdo}
|
||||
view wave
|
||||
view structure
|
||||
view signals
|
||||
run 10us
|
||||
## End
|
||||
@@ -0,0 +1,33 @@
|
||||
onerror {resume}
|
||||
quietly WaveActivateNextPane {} 0
|
||||
add wave -noupdate -format Literal /tb_syn_nco/freq_word
|
||||
add wave -noupdate -format Literal /tb_syn_nco/dfreq_word
|
||||
add wave -noupdate -format Logic /tb_syn_nco/clk
|
||||
add wave -noupdate -format Logic /tb_syn_nco/srst
|
||||
add wave -noupdate -format Logic /tb_syn_nco/pacc_clr
|
||||
add wave -noupdate -format Logic /tb_syn_nco/pacc_inc
|
||||
add wave -noupdate -format Logic /tb_syn_nco/phase_load
|
||||
add wave -noupdate -format Logic /tb_syn_nco/freq_load
|
||||
add wave -noupdate -format Literal -radix decimal /tb_syn_nco/freq_in
|
||||
add wave -noupdate -format Literal -radix decimal /tb_syn_nco/phase_in
|
||||
add wave -noupdate -format Analog-Step -radix decimal -scale 0.004884004884004884 /tb_syn_nco/wave_out_i
|
||||
add wave -noupdate -format Analog-Step -radix decimal -scale 0.004884004884004884 /tb_syn_nco/wave_out_q
|
||||
add wave -noupdate -format Logic /tb_syn_nco/out_valid
|
||||
add wave -noupdate -format Analog-Step -radix decimal -scale 0.00030518043793392844 /tb_syn_nco/phase_out
|
||||
add wave -noupdate -format Logic /tb_syn_nco/fileout_enable
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 1} {4737111 ps} 0}
|
||||
configure wave -namecolwidth 193
|
||||
configure wave -valuecolwidth 100
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 1
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
configure wave -gridoffset 0
|
||||
configure wave -gridperiod 1
|
||||
configure wave -griddelta 40
|
||||
configure wave -timeline 0
|
||||
update
|
||||
WaveRestoreZoom {4171440 ps} {5483940 ps}
|
||||
Binary file not shown.
@@ -0,0 +1,8 @@
|
||||
function wav2in(name)
|
||||
|
||||
x = wavread(name)*(2^15);
|
||||
|
||||
fid = fopen('wav_in.dat', 'w');
|
||||
fwrite(fid, fix(x), 'int');
|
||||
fclose(fid);
|
||||
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
@@ -0,0 +1,181 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 17:16:42 13.05.2007
|
||||
-- Design Name: tb_nco
|
||||
-- Module Name: tb_nco.vhd
|
||||
-- Project Name: nco
|
||||
-- Target Device:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.MATH_REAL.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
use std.textio.all; -- Imports the standard textio package.
|
||||
|
||||
library work;
|
||||
use work.fixed_pkg.all;
|
||||
use work.filter_pkg.all;
|
||||
use work.fir_stage_pkg.all;
|
||||
use work.fir_iterative_pkg.all;
|
||||
|
||||
ENTITY syn_fir_iterative IS
|
||||
Generic (
|
||||
ntaps : integer := 501;
|
||||
nbits_in : integer := 18;
|
||||
nbits_in_frac : integer := 18;
|
||||
nbits_stages : integer := 20;
|
||||
nbits_stages_frac : integer := 18;
|
||||
nbits_out : integer := 18;
|
||||
nbits_out_frac : integer := 18;
|
||||
fir_mode : fir_iterative_mode_t := symmetric;
|
||||
rounding : boolean := true;
|
||||
saturating : boolean := true
|
||||
);
|
||||
PORT(
|
||||
rst : in std_logic;
|
||||
clk : in std_logic;
|
||||
ready_i : out std_logic;
|
||||
x_valid_i : in std_logic;
|
||||
x_din_i : in signed(nbits_in-1 downto 0);
|
||||
y_valid_i : out std_logic;
|
||||
y_dout_i : out signed(nbits_out-1 downto 0);
|
||||
ready_q : out std_logic;
|
||||
x_valid_q : in std_logic;
|
||||
x_din_q : in signed(nbits_in-1 downto 0);
|
||||
y_valid_q : out std_logic;
|
||||
y_dout_q : out signed(nbits_out-1 downto 0)
|
||||
);
|
||||
END syn_fir_iterative;
|
||||
|
||||
ARCHITECTURE behavior OF syn_fir_iterative IS
|
||||
|
||||
-- Component Declaration for the Unit Under Test (UUT)
|
||||
COMPONENT fir_iterative
|
||||
GENERIC
|
||||
(
|
||||
ntaps : integer;
|
||||
nbits_in : integer;
|
||||
nbits_in_frac : integer;
|
||||
nbits_stages : integer;
|
||||
nbits_stages_frac : integer;
|
||||
nbits_out : integer;
|
||||
nbits_out_frac : integer;
|
||||
fir_mode : fir_iterative_mode_t;
|
||||
rounding : boolean;
|
||||
saturating : boolean
|
||||
);
|
||||
PORT
|
||||
(
|
||||
srst : in std_logic;
|
||||
clk : in std_logic;
|
||||
h_din : in sfixed;
|
||||
h_addr_out : out unsigned(taps_nbits(ntaps, fir_mode)-1 downto 0);
|
||||
ready : out std_logic;
|
||||
x_valid : in std_logic;
|
||||
x_din : in sfixed;
|
||||
y_dout_valid : out std_logic;
|
||||
y_dout : out sfixed
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
type h_mem_t is array (0 to ntaps-1) of sfixed(sproto(nbits_stages, nbits_stages_frac)'high downto sproto(nbits_stages, nbits_stages_frac)'low);
|
||||
|
||||
function to_h_mem(coef_real : real_array_t; ntaps : integer; proto : sfixed) return h_mem_t is
|
||||
variable res : h_mem_t;
|
||||
begin
|
||||
for i in 0 to ntaps-1 loop
|
||||
res(i) := to_sfixed(coef_real(i), proto);
|
||||
end loop;
|
||||
|
||||
return res;
|
||||
end to_h_mem;
|
||||
|
||||
|
||||
--Outputs
|
||||
SIGNAL h_i, h_q : sfixed(sproto(nbits_stages, nbits_stages_frac)'high downto sproto(nbits_stages, nbits_stages_frac)'low);
|
||||
SIGNAL x_i, x_q : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low);
|
||||
SIGNAL y_i, y_q : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low);
|
||||
SIGNAL h_addr_i, h_addr_q : unsigned(taps_nbits(ntaps, fir_mode)-1 downto 0);
|
||||
|
||||
-- ROM
|
||||
CONSTANT coeffs : real_array_t(0 to ntaps_addr(ntaps, fir_mode)-1) := FilterCoef_Lowpass(ntaps_addr(ntaps, fir_mode), 0.05, 0.05);
|
||||
CONSTANT h_mem : h_mem_t := to_h_mem(coeffs, ntaps_addr(ntaps, fir_mode), h_i);
|
||||
|
||||
|
||||
BEGIN
|
||||
|
||||
-- Instantiate the Unit Under Test (UUT)
|
||||
inst_fir_iterative_i: fir_iterative
|
||||
GENERIC MAP
|
||||
(
|
||||
ntaps => ntaps,
|
||||
nbits_in => nbits_in,
|
||||
nbits_in_frac => nbits_in_frac,
|
||||
nbits_out => nbits_out,
|
||||
nbits_out_frac => nbits_out_frac,
|
||||
nbits_stages => nbits_stages,
|
||||
nbits_stages_frac => nbits_stages_frac,
|
||||
fir_mode => fir_mode,
|
||||
rounding => rounding,
|
||||
saturating => saturating
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
srst => rst,
|
||||
clk => clk,
|
||||
h_din => h_i,
|
||||
h_addr_out => h_addr_i,
|
||||
ready => ready_i,
|
||||
x_valid => x_valid_i,
|
||||
x_din => x_i,
|
||||
y_dout_valid => y_valid_i,
|
||||
y_dout => y_i
|
||||
);
|
||||
|
||||
inst_fir_iterative_q: fir_iterative
|
||||
GENERIC MAP
|
||||
(
|
||||
ntaps => ntaps,
|
||||
nbits_in => nbits_in,
|
||||
nbits_in_frac => nbits_in_frac,
|
||||
nbits_out => nbits_out,
|
||||
nbits_out_frac => nbits_out_frac,
|
||||
nbits_stages => nbits_stages,
|
||||
nbits_stages_frac => nbits_stages_frac,
|
||||
fir_mode => fir_mode,
|
||||
rounding => rounding,
|
||||
saturating => saturating
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
srst => rst,
|
||||
clk => clk,
|
||||
h_din => h_q,
|
||||
h_addr_out => h_addr_q,
|
||||
ready => ready_q,
|
||||
x_valid => x_valid_q,
|
||||
x_din => x_q,
|
||||
y_dout_valid => y_valid_Q,
|
||||
y_dout => y_q
|
||||
);
|
||||
|
||||
x_i <= to_sfixed(x_din_i, x_i);
|
||||
y_dout_i <= signed(y_i);
|
||||
|
||||
x_q <= to_sfixed(x_din_q, x_q);
|
||||
y_dout_q <= signed(y_q);
|
||||
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
h_i <= h_mem(to_integer(h_addr_i));
|
||||
h_q <= h_mem(to_integer(h_addr_q));
|
||||
end if;
|
||||
end process;
|
||||
|
||||
END;
|
||||
@@ -0,0 +1,130 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 17:16:42 13.05.2007
|
||||
-- Design Name: tb_mix_cpx
|
||||
-- Module Name: tb_mix_cpx.vhd
|
||||
-- Project Name: mix_cpx
|
||||
-- Target Device:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.MATH_REAL.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
use std.textio.all; -- Imports the standard textio package.
|
||||
|
||||
library work;
|
||||
use work.fixed_pkg.all;
|
||||
use work.mix_cpx_pkg.all;
|
||||
|
||||
ENTITY syn_mix_cpx IS
|
||||
Generic (
|
||||
nbits_in : integer := 12;
|
||||
nbits_in_frac : integer := 12;
|
||||
nbits_out : integer := 12;
|
||||
nbits_out_frac : integer := 12;
|
||||
has_in_reg : boolean := true;
|
||||
has_pipe_reg : boolean := true;
|
||||
has_out_reg : boolean := true;
|
||||
rounding : boolean := true;
|
||||
saturating : boolean := false
|
||||
);
|
||||
Port
|
||||
(
|
||||
sys_rst : in std_logic;
|
||||
sys_clk : in std_logic;
|
||||
sys_in_valid : in std_logic;
|
||||
sys_x_re_in : in signed(nbits_in-1 downto 0);
|
||||
sys_x_im_in : in signed(nbits_in-1 downto 0);
|
||||
sys_y_re_in : in signed(nbits_in-1 downto 0);
|
||||
sys_y_im_in : in signed(nbits_in-1 downto 0);
|
||||
sys_out_valid : out std_logic;
|
||||
sys_z_re_out : out signed(nbits_out-1 downto 0);
|
||||
sys_z_im_out : out signed(nbits_out-1 downto 0)
|
||||
);
|
||||
END syn_mix_cpx;
|
||||
|
||||
ARCHITECTURE behavior OF syn_mix_cpx IS
|
||||
|
||||
-- Component Declaration for the Unit Under Test (UUT)
|
||||
COMPONENT mix_cpx
|
||||
GENERIC
|
||||
(
|
||||
nbits_in : integer;
|
||||
nbits_in_frac : integer;
|
||||
nbits_out : integer;
|
||||
nbits_out_frac : integer;
|
||||
has_in_reg : boolean;
|
||||
has_pipe_reg : boolean;
|
||||
has_out_reg : boolean;
|
||||
rounding : boolean;
|
||||
saturating : boolean
|
||||
);
|
||||
PORT
|
||||
(
|
||||
srst : in std_logic;
|
||||
clk : in std_logic;
|
||||
in_valid : in std_logic;
|
||||
x_re_in : in sfixed;
|
||||
x_im_in : in sfixed;
|
||||
y_re_in : in sfixed;
|
||||
y_im_in : in sfixed;
|
||||
out_valid : out std_logic;
|
||||
z_re_out : out sfixed;
|
||||
z_im_out : out sfixed
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
--Inputs
|
||||
SIGNAL x_re_in : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low);
|
||||
SIGNAL x_im_in : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low);
|
||||
SIGNAL y_re_in : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low);
|
||||
SIGNAL y_im_in : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low);
|
||||
|
||||
--Outputs
|
||||
SIGNAL z_re_out : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low);
|
||||
SIGNAL z_im_out : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low);
|
||||
|
||||
|
||||
BEGIN
|
||||
|
||||
-- Instantiate the Unit Under Test (UUT)
|
||||
inst_mix_cpx: mix_cpx
|
||||
GENERIC MAP
|
||||
(
|
||||
nbits_in => nbits_in,
|
||||
nbits_in_frac => nbits_in_frac,
|
||||
nbits_out => nbits_out,
|
||||
nbits_out_frac => nbits_out_frac,
|
||||
has_in_reg => has_in_reg,
|
||||
has_pipe_reg => has_pipe_reg,
|
||||
has_out_reg => has_out_reg,
|
||||
rounding => rounding,
|
||||
saturating => saturating
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
srst => sys_rst,
|
||||
clk => sys_clk,
|
||||
in_valid => sys_in_valid,
|
||||
x_re_in => x_re_in,
|
||||
x_im_in => x_im_in,
|
||||
y_re_in => y_re_in,
|
||||
y_im_in => y_im_in,
|
||||
out_valid => sys_out_valid,
|
||||
z_re_out => z_re_out,
|
||||
z_im_out => z_im_out
|
||||
);
|
||||
|
||||
x_re_in <= sfixed(sys_x_re_in);
|
||||
x_im_in <= sfixed(sys_x_im_in);
|
||||
y_re_in <= sfixed(sys_y_re_in);
|
||||
y_im_in <= sfixed(sys_y_im_in);
|
||||
sys_z_re_out <= signed(z_re_out);
|
||||
sys_z_im_out <= signed(z_im_out);
|
||||
|
||||
END;
|
||||
@@ -0,0 +1,114 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 17:16:42 13.05.2007
|
||||
-- Design Name: tb_nco
|
||||
-- Module Name: tb_nco.vhd
|
||||
-- Project Name: nco
|
||||
-- Target Device:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.MATH_REAL.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
use std.textio.all; -- Imports the standard textio package.
|
||||
|
||||
library work;
|
||||
use work.fixed_pkg.all;
|
||||
use work.nco_pkg.all;
|
||||
|
||||
ENTITY syn_nco IS
|
||||
Generic (
|
||||
nbits_wave : integer := 12;
|
||||
nbits_phase : integer := 16;
|
||||
nbits_lut_depth : integer := 8;
|
||||
nbits_dither : integer := 5;
|
||||
has_pipe_reg : boolean := true;
|
||||
has_out_reg : boolean := true
|
||||
);
|
||||
PORT(
|
||||
sys_rst : in std_logic;
|
||||
sys_clk : in std_logic;
|
||||
sys_pacc_clr : in std_logic;
|
||||
sys_pacc_inc : in std_logic;
|
||||
sys_freq_in : in unsigned(nbits_phase-1 downto 0);
|
||||
sys_freq_load : in std_logic;
|
||||
sys_phase_in : in unsigned(nbits_phase-1 downto 0);
|
||||
sys_phase_load : in std_logic;
|
||||
sys_phase_out : out unsigned(nbits_phase-1 downto 0);
|
||||
sys_wave_out_i : out signed(nbits_wave-1 downto 0);
|
||||
sys_wave_out_q : out signed(nbits_wave-1 downto 0);
|
||||
sys_out_valid : out std_logic
|
||||
);
|
||||
END syn_nco;
|
||||
|
||||
ARCHITECTURE behavior OF syn_nco IS
|
||||
|
||||
-- Component Declaration for the Unit Under Test (UUT)
|
||||
COMPONENT nco
|
||||
GENERIC (
|
||||
nbits_wave : integer;
|
||||
nbits_phase : integer;
|
||||
nbits_lut_depth : integer;
|
||||
nbits_dither : integer;
|
||||
has_pipe_reg : boolean;
|
||||
has_out_reg : boolean
|
||||
);
|
||||
PORT(
|
||||
srst : in std_logic;
|
||||
clk : in std_logic;
|
||||
pacc_clr : in std_logic;
|
||||
pacc_inc : in std_logic;
|
||||
freq_in : in unsigned(nbits_phase-1 downto 0);
|
||||
freq_load : in std_logic;
|
||||
phase_in : in unsigned(nbits_phase-1 downto 0);
|
||||
phase_load : in std_logic;
|
||||
phase_out : out unsigned(nbits_phase-1 downto 0);
|
||||
wave_out_i : out sfixed;
|
||||
wave_out_q : out sfixed;
|
||||
out_valid : out std_logic
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
--Constants
|
||||
constant nbits_wave_frac : integer := nbits_wave;
|
||||
|
||||
--Outputs
|
||||
SIGNAL wave_i : sfixed(sproto(nbits_wave, nbits_wave_frac)'high downto sproto(nbits_wave, nbits_wave_frac)'low);
|
||||
SIGNAL wave_q : sfixed(sproto(nbits_wave, nbits_wave_frac)'high downto sproto(nbits_wave, nbits_wave_frac)'low);
|
||||
|
||||
BEGIN
|
||||
|
||||
-- Instantiate the Unit Under Test (UUT)
|
||||
inst_nco: nco
|
||||
GENERIC MAP (
|
||||
nbits_wave => nbits_wave,
|
||||
nbits_phase => nbits_phase,
|
||||
nbits_lut_depth => nbits_lut_depth,
|
||||
nbits_dither => nbits_dither,
|
||||
has_pipe_reg => has_pipe_reg,
|
||||
has_out_reg => has_out_reg
|
||||
)
|
||||
PORT MAP(
|
||||
srst => sys_rst,
|
||||
clk => sys_clk,
|
||||
pacc_clr => sys_pacc_clr,
|
||||
pacc_inc => sys_pacc_inc,
|
||||
freq_in => sys_freq_in,
|
||||
freq_load => sys_freq_load,
|
||||
phase_in => sys_phase_in,
|
||||
phase_load => sys_phase_load,
|
||||
phase_out => sys_phase_out,
|
||||
wave_out_i => wave_i,
|
||||
wave_out_q => wave_q,
|
||||
out_valid => sys_out_valid
|
||||
);
|
||||
|
||||
sys_wave_out_i <= signed(wave_i);
|
||||
sys_wave_out_q <= signed(wave_q);
|
||||
|
||||
END;
|
||||
@@ -0,0 +1,182 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 17:16:42 13.05.2007
|
||||
-- Design Name: tb_mix_cpx
|
||||
-- Module Name: tb_mix_cpx.vhd
|
||||
-- Project Name: mix_cpx
|
||||
-- Target Device:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.MATH_REAL.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
use std.textio.all; -- Imports the standard textio package.
|
||||
|
||||
library work;
|
||||
use work.fixed_pkg.all;
|
||||
use work.mix_pkg.all;
|
||||
|
||||
ENTITY tb_syn_mix_cpx IS
|
||||
Generic (
|
||||
nbits_in : integer := 12;
|
||||
nbits_in_frac : integer := 12;
|
||||
nbits_out : integer := 12;
|
||||
nbits_out_frac : integer := 12;
|
||||
has_in_reg : boolean := true;
|
||||
has_pipe_reg : boolean := true;
|
||||
has_out_reg : boolean := true;
|
||||
rounding : boolean := true;
|
||||
saturating : boolean := true
|
||||
);
|
||||
END tb_syn_mix_cpx;
|
||||
|
||||
ARCHITECTURE behavior OF tb_syn_mix_cpx IS
|
||||
|
||||
-- Component Declaration for the Unit Under Test (UUT)
|
||||
COMPONENT syn_mix_cpx
|
||||
GENERIC
|
||||
(
|
||||
nbits_in : integer;
|
||||
nbits_in_frac : integer;
|
||||
nbits_out : integer;
|
||||
nbits_out_frac : integer;
|
||||
has_in_reg : boolean;
|
||||
has_pipe_reg : boolean;
|
||||
has_out_reg : boolean;
|
||||
rounding : boolean;
|
||||
saturating : boolean
|
||||
);
|
||||
PORT
|
||||
(
|
||||
sys_rst : in std_logic;
|
||||
sys_clk : in std_logic;
|
||||
sys_in_valid : in std_logic;
|
||||
sys_x_re_in : in signed;
|
||||
sys_x_im_in : in signed;
|
||||
sys_y_re_in : in signed;
|
||||
sys_y_im_in : in signed;
|
||||
sys_out_valid : out std_logic;
|
||||
sys_z_re_out : out signed;
|
||||
sys_z_im_out : out signed
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
--Constants
|
||||
constant PERIOD : time := 10 ns;
|
||||
|
||||
|
||||
--Inputs
|
||||
SIGNAL clk : std_logic := '0';
|
||||
SIGNAL srst : std_logic := '1';
|
||||
SIGNAL in_valid : std_logic := '0';
|
||||
SIGNAL x_re_in : signed(nbits_in-1 downto 0);
|
||||
SIGNAL x_im_in : signed(nbits_in-1 downto 0);
|
||||
SIGNAL y_re_in : signed(nbits_in-1 downto 0);
|
||||
SIGNAL y_im_in : signed(nbits_in-1 downto 0);
|
||||
|
||||
--Outputs
|
||||
SIGNAL z_re_out : signed(nbits_out-1 downto 0);
|
||||
SIGNAL z_im_out : signed(nbits_out-1 downto 0);
|
||||
SIGNAL out_valid : std_logic;
|
||||
|
||||
SIGNAL x_re : real := 0.0;
|
||||
SIGNAL x_im : real := 0.0;
|
||||
SIGNAL y_re : real := 0.0;
|
||||
SIGNAL y_im : real := 0.0;
|
||||
SIGNAL z_re : real := 0.0;
|
||||
SIGNAL z_im : real := 0.0;
|
||||
|
||||
BEGIN
|
||||
|
||||
-- Instantiate the Unit Under Test (UUT)
|
||||
uut: syn_mix_cpx
|
||||
GENERIC MAP
|
||||
(
|
||||
nbits_in => nbits_in,
|
||||
nbits_in_frac => nbits_in_frac,
|
||||
nbits_out => nbits_out,
|
||||
nbits_out_frac => nbits_out_frac,
|
||||
has_in_reg => has_in_reg,
|
||||
has_pipe_reg => has_pipe_reg,
|
||||
has_out_reg => has_out_reg,
|
||||
rounding => rounding,
|
||||
saturating => saturating
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
sys_rst => srst,
|
||||
sys_clk => clk,
|
||||
sys_in_valid => in_valid,
|
||||
sys_x_re_in => x_re_in,
|
||||
sys_x_im_in => x_im_in,
|
||||
sys_y_re_in => y_re_in,
|
||||
sys_y_im_in => y_im_in,
|
||||
sys_out_valid => out_valid,
|
||||
sys_z_re_out => z_re_out,
|
||||
sys_z_im_out => z_im_out
|
||||
);
|
||||
|
||||
tb_clk : PROCESS
|
||||
BEGIN
|
||||
clk <= not clk;
|
||||
wait for PERIOD/2;
|
||||
END PROCESS;
|
||||
|
||||
tb : PROCESS
|
||||
|
||||
BEGIN
|
||||
|
||||
-- Wait 100 ns for global reset to finish
|
||||
wait for 4*PERIOD;
|
||||
srst <= '0';
|
||||
------------------------------------------
|
||||
wait for 2*PERIOD;
|
||||
wait until rising_edge(clk);
|
||||
x_re_in <= signed(to_sfixed(0.5, sproto(nbits_in, nbits_in_frac)));
|
||||
x_im_in <= signed(to_sfixed(0.5, sproto(nbits_in, nbits_in_frac)));
|
||||
y_re_in <= signed(to_sfixed(0.5, sproto(nbits_in, nbits_in_frac)));
|
||||
y_im_in <= signed(to_sfixed(0.5, sproto(nbits_in, nbits_in_frac)));
|
||||
in_valid <= '1';
|
||||
------------------------------------------
|
||||
wait until rising_edge(clk);
|
||||
x_re_in <= signed(to_sfixed(0.125, sproto(nbits_in, nbits_in_frac)));
|
||||
x_im_in <= signed(to_sfixed(0.25, sproto(nbits_in, nbits_in_frac)));
|
||||
y_re_in <= signed(to_sfixed(0.25, sproto(nbits_in, nbits_in_frac)));
|
||||
y_im_in <= signed(to_sfixed(0.125, sproto(nbits_in, nbits_in_frac)));
|
||||
in_valid <= '1';
|
||||
------------------------------------------
|
||||
wait until rising_edge(clk);
|
||||
x_re_in <= signed(to_sfixed(0.125, sproto(nbits_in, nbits_in_frac)));
|
||||
x_im_in <= signed(to_sfixed(-0.25, sproto(nbits_in, nbits_in_frac)));
|
||||
y_re_in <= signed(to_sfixed(0.25, sproto(nbits_in, nbits_in_frac)));
|
||||
y_im_in <= signed(to_sfixed(0.125, sproto(nbits_in, nbits_in_frac)));
|
||||
in_valid <= '1';
|
||||
------------------------------------------
|
||||
wait until rising_edge(clk);
|
||||
x_re_in <= signed(to_sfixed(0.125, sproto(nbits_in, nbits_in_frac)));
|
||||
x_im_in <= signed(to_sfixed(0.25, sproto(nbits_in, nbits_in_frac)));
|
||||
y_re_in <= signed(to_sfixed(0.25, sproto(nbits_in, nbits_in_frac)));
|
||||
y_im_in <= signed(to_sfixed(-0.125, sproto(nbits_in, nbits_in_frac)));
|
||||
in_valid <= '1';
|
||||
wait until rising_edge(clk);
|
||||
in_valid <= '0';
|
||||
|
||||
wait for 20*PERIOD;
|
||||
|
||||
assert false report "Test finished" severity error;
|
||||
wait;
|
||||
END PROCESS;
|
||||
|
||||
x_re <= to_real(sfixed(x_re_in));
|
||||
x_im <= to_real(sfixed(x_im_in));
|
||||
y_re <= to_real(sfixed(y_re_in));
|
||||
y_im <= to_real(sfixed(y_im_in));
|
||||
z_re <= to_real(sfixed(z_re_out));
|
||||
z_im <= to_real(sfixed(z_im_out));
|
||||
|
||||
END;
|
||||
@@ -0,0 +1,282 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 17:16:42 13.05.2007
|
||||
-- Design Name: tb_nco
|
||||
-- Module Name: tb_nco.vhd
|
||||
-- Project Name: nco
|
||||
-- Target Device:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.MATH_REAL.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
use std.textio.all; -- Imports the standard textio package.
|
||||
|
||||
library work;
|
||||
use work.fixed_pkg.all;
|
||||
use work.nco_pkg.all;
|
||||
--use work.PCK_FIO.all;
|
||||
|
||||
ENTITY tb_syn_nco IS
|
||||
Generic (
|
||||
nbits_wave : integer := 12;
|
||||
nbits_phase : integer := 16;
|
||||
nbits_lut_depth : integer := 12;
|
||||
nbits_dither : integer := 5;
|
||||
has_pipe_reg : boolean := true;
|
||||
has_out_reg : boolean := true
|
||||
);
|
||||
END tb_syn_nco;
|
||||
|
||||
ARCHITECTURE behavior OF tb_syn_nco IS
|
||||
|
||||
-- Component Declaration for the Unit Under Test (UUT)
|
||||
COMPONENT syn_nco
|
||||
GENERIC (
|
||||
nbits_wave : integer;
|
||||
nbits_phase : integer;
|
||||
nbits_lut_depth : integer;
|
||||
nbits_dither : integer;
|
||||
has_pipe_reg : boolean;
|
||||
has_out_reg : boolean
|
||||
);
|
||||
PORT(
|
||||
sys_rst : in std_logic;
|
||||
sys_clk : in std_logic;
|
||||
sys_pacc_clr : in std_logic;
|
||||
sys_pacc_inc : in std_logic;
|
||||
sys_freq_in : in unsigned(nbits_phase-1 downto 0);
|
||||
sys_freq_load : in std_logic;
|
||||
sys_phase_in : in unsigned(nbits_phase-1 downto 0);
|
||||
sys_phase_load : in std_logic;
|
||||
sys_phase_out : out unsigned(nbits_phase-1 downto 0);
|
||||
sys_wave_out_i : out signed(nbits_wave-1 downto 0);
|
||||
sys_wave_out_q : out signed(nbits_wave-1 downto 0);
|
||||
sys_out_valid : out std_logic
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
--Constants
|
||||
constant f : REAL := 10.2E6;
|
||||
constant df : REAL := 10.0E3;
|
||||
constant fa : REAL := 100.0E6;
|
||||
constant PERIOD : time := 10 ns;
|
||||
constant nbits_wave_frac : integer := nbits_wave;
|
||||
|
||||
SIGNAL freq_word : integer := integer(f/fa*2.0**nbits_phase);
|
||||
SIGNAL dfreq_word : integer := integer(df/fa*2.0**nbits_phase);
|
||||
|
||||
--Inputs
|
||||
SIGNAL clk : std_logic := '0';
|
||||
SIGNAL srst : std_logic := '1';
|
||||
SIGNAL pacc_clr : std_logic := '0';
|
||||
SIGNAL pacc_inc : std_logic := '0';
|
||||
SIGNAL phase_load : std_logic := '0';
|
||||
SIGNAL freq_load : std_logic := '0';
|
||||
SIGNAL freq_in : unsigned(nbits_phase-1 downto 0);
|
||||
SIGNAL phase_in : unsigned(nbits_phase-1 downto 0);
|
||||
|
||||
--Outputs
|
||||
SIGNAL wave_out_i : signed(nbits_wave-1 downto 0);
|
||||
SIGNAL wave_out_q : signed(nbits_wave-1 downto 0);
|
||||
SIGNAL out_valid : std_logic;
|
||||
SIGNAL phase_out : unsigned(nbits_phase-1 downto 0);
|
||||
|
||||
SIGNAL fileout_enable : std_logic := '0';
|
||||
|
||||
BEGIN
|
||||
|
||||
-- Instantiate the Unit Under Test (UUT)
|
||||
uut: syn_nco
|
||||
GENERIC MAP (
|
||||
nbits_wave => nbits_wave,
|
||||
nbits_phase => nbits_phase,
|
||||
nbits_lut_depth => nbits_lut_depth,
|
||||
nbits_dither => nbits_dither,
|
||||
has_pipe_reg => has_pipe_reg,
|
||||
has_out_reg => has_out_reg
|
||||
)
|
||||
PORT MAP(
|
||||
sys_rst => srst,
|
||||
sys_clk => clk,
|
||||
sys_pacc_clr => pacc_clr,
|
||||
sys_pacc_inc => pacc_inc,
|
||||
sys_freq_in => freq_in,
|
||||
sys_freq_load => freq_load,
|
||||
sys_phase_in => phase_in,
|
||||
sys_phase_load => phase_load,
|
||||
sys_phase_out => phase_out,
|
||||
sys_wave_out_i => wave_out_i,
|
||||
sys_wave_out_q => wave_out_q,
|
||||
sys_out_valid => out_valid
|
||||
);
|
||||
|
||||
tb_clk : PROCESS
|
||||
BEGIN
|
||||
clk <= not clk;
|
||||
wait for PERIOD/2;
|
||||
END PROCESS;
|
||||
|
||||
tb : PROCESS
|
||||
|
||||
BEGIN
|
||||
|
||||
-- Wait 100 ns for global reset to finish
|
||||
wait for 4*PERIOD;
|
||||
srst <= '0';
|
||||
|
||||
wait for 2*PERIOD;
|
||||
-------------------------------------------
|
||||
-- 1
|
||||
freq_in <= to_unsigned(0,nbits_phase);
|
||||
wait until rising_edge(clk);
|
||||
phase_load <= '1';
|
||||
wait until rising_edge(clk);
|
||||
phase_load <= '0';
|
||||
|
||||
freq_in <= to_unsigned(1411,nbits_phase);
|
||||
wait until rising_edge(clk);
|
||||
freq_load <= '1';
|
||||
wait until rising_edge(clk);
|
||||
freq_load <= '0';
|
||||
|
||||
wait for 2*PERIOD;
|
||||
pacc_inc <= '1';
|
||||
|
||||
wait for 2*PERIOD;
|
||||
wait until rising_edge(clk);
|
||||
|
||||
wait for 40*PERIOD;
|
||||
-------------------------------------------
|
||||
freq_in <= to_unsigned(643,nbits_phase);
|
||||
wait until rising_edge(clk);
|
||||
freq_load <= '1';
|
||||
wait until rising_edge(clk);
|
||||
freq_load <= '0';
|
||||
|
||||
wait for 40*PERIOD;
|
||||
-------------------------------------------
|
||||
phase_in <= to_unsigned(800,nbits_phase);
|
||||
wait until rising_edge(clk);
|
||||
phase_load <= '1';
|
||||
wait until rising_edge(clk);
|
||||
phase_load <= '0';
|
||||
|
||||
wait for 20*PERIOD;
|
||||
-------------------------------------------
|
||||
phase_in <= to_unsigned(45072,nbits_phase);
|
||||
wait until rising_edge(clk);
|
||||
phase_load <= '1';
|
||||
wait until rising_edge(clk);
|
||||
phase_load <= '0';
|
||||
|
||||
wait for 20*PERIOD;
|
||||
-------------------------------------------
|
||||
phase_in <= to_unsigned(20593,nbits_phase);
|
||||
wait until rising_edge(clk);
|
||||
phase_load <= '1';
|
||||
wait until rising_edge(clk);
|
||||
phase_load <= '0';
|
||||
|
||||
-------------------------------------------
|
||||
freq_in <= to_unsigned(freq_word,nbits_phase);
|
||||
wait until rising_edge(clk);
|
||||
freq_load <= '1';
|
||||
wait until rising_edge(clk);
|
||||
freq_load <= '0';
|
||||
|
||||
wait for 20*PERIOD;
|
||||
fileout_enable <= '1';
|
||||
|
||||
wait for 20000*PERIOD;
|
||||
fileout_enable <= '0';
|
||||
|
||||
-------------------------------------------
|
||||
-- Sweep
|
||||
freq_word <= 100;
|
||||
for i in 1 to 200 loop
|
||||
wait for 20*PERIOD;
|
||||
freq_word <= freq_word + dfreq_word;
|
||||
|
||||
freq_in <= to_unsigned(freq_word,nbits_phase);
|
||||
wait until rising_edge(clk);
|
||||
freq_load <= '1';
|
||||
wait until rising_edge(clk);
|
||||
freq_load <= '0';
|
||||
|
||||
end loop;
|
||||
|
||||
pacc_inc <= '0';
|
||||
wait for 20*PERIOD;
|
||||
fileout_enable <= '0';
|
||||
wait until rising_edge(clk);
|
||||
pacc_clr <= '1';
|
||||
wait until rising_edge(clk);
|
||||
pacc_clr <= '0';
|
||||
wait for 20*PERIOD;
|
||||
pacc_inc <= '1';
|
||||
wait for 20*PERIOD;
|
||||
wait until rising_edge(clk);
|
||||
pacc_clr <= '1';
|
||||
wait until rising_edge(clk);
|
||||
pacc_clr <= '0';
|
||||
wait for 20*PERIOD;
|
||||
pacc_inc <= '0';
|
||||
wait for 20*PERIOD;
|
||||
wait until rising_edge(clk);
|
||||
pacc_inc <= '1';
|
||||
wait until rising_edge(clk);
|
||||
pacc_inc <= '0';
|
||||
wait for 20*PERIOD;
|
||||
wait until rising_edge(clk);
|
||||
srst <= '1';
|
||||
wait until rising_edge(clk);
|
||||
srst <= '0';
|
||||
freq_in <= to_unsigned(freq_word,nbits_phase);
|
||||
wait until rising_edge(clk);
|
||||
freq_load <= '1';
|
||||
wait until rising_edge(clk);
|
||||
freq_load <= '0';
|
||||
|
||||
wait for 20*PERIOD;
|
||||
pacc_inc <= '1';
|
||||
wait for 20*PERIOD;
|
||||
wait until rising_edge(clk);
|
||||
srst <= '1';
|
||||
wait until rising_edge(clk);
|
||||
srst <= '0';
|
||||
wait for 20*PERIOD;
|
||||
pacc_inc <= '0';
|
||||
|
||||
wait for 20*PERIOD;
|
||||
|
||||
assert false report "Test finished" severity error;
|
||||
wait;
|
||||
END PROCESS;
|
||||
|
||||
-- tb_fo : PROCESS(clk, fileout_enable, out_valid)
|
||||
-- file RESULT_I: text open write_mode is "i_ud.txt";
|
||||
-- file RESULT_Q: text open write_mode is "q_ud.txt";
|
||||
-- file RESULT_ID: text open write_mode is "i_d.txt";
|
||||
-- file RESULT_QD: text open write_mode is "q_d.txt";
|
||||
-- file RESULT_LFSR: text open write_mode is "lfsr.txt";
|
||||
--- variable L: line;
|
||||
|
||||
-- BEGIN
|
||||
-- if rising_edge(clk) and fileout_enable = '1' and out_valid = '1' then
|
||||
-- fprint(RESULT_I, L,"%s\n", REAL'image(debug_out.i_ud));
|
||||
-- fprint(RESULT_Q, L,"%s\n", REAL'image(debug_out.q_ud));
|
||||
-- fprint(RESULT_ID, L,"%s\n", REAL'image(debug_out.i_d));
|
||||
-- fprint(RESULT_QD, L,"%s\n", REAL'image(debug_out.q_d));
|
||||
-- fprint(RESULT_LFSR, L,"%s\n", INTEGER'image(to_integer(debug_out.lfsr)));
|
||||
-- end if;
|
||||
|
||||
-- END PROCESS;
|
||||
|
||||
|
||||
END;
|
||||
@@ -0,0 +1,63 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: Dual-ported register file with asynchrous read
|
||||
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
|
||||
-- This library is free software; you can redistribute it and/or
|
||||
-- modify it under the terms of the GNU Lesser General Public
|
||||
-- License as published by the Free Software Foundation; either
|
||||
-- version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
-- This library is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
-- Lesser General Public License for more details.
|
||||
|
||||
-- You should have received a copy of the GNU Lesser General Public
|
||||
-- License along with this library; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.numeric_std.ALL;
|
||||
|
||||
entity xmem_dual is
|
||||
Generic (
|
||||
addr_width : integer := 3;
|
||||
data_width : integer := 8
|
||||
);
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
we : in STD_LOGIC;
|
||||
addr_w : in unsigned (addr_width-1 downto 0);
|
||||
addr_r : in unsigned (addr_width-1 downto 0);
|
||||
din : in unsigned (data_width-1 downto 0);
|
||||
dout : out unsigned (data_width-1 downto 0)
|
||||
);
|
||||
end xmem_dual;
|
||||
|
||||
architecture Behavioral of xmem_dual is
|
||||
|
||||
constant depth : integer := 2**addr_width;
|
||||
type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
|
||||
signal RAM : RAMtype;
|
||||
|
||||
begin
|
||||
|
||||
process (clk)
|
||||
begin
|
||||
if clk'event and clk = '1' then
|
||||
if we = '1' then
|
||||
RAM(to_integer(addr_w)) <= din;
|
||||
end if;
|
||||
dout <= RAM(to_integer(addr_r));
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end Behavioral;
|
||||
|
||||
@@ -0,0 +1 @@
|
||||
work
|
||||
@@ -0,0 +1,7 @@
|
||||
vhdl work "../../../../lib/fixed/fixed_pkg_c.vhd"
|
||||
vhdl work "../../src/filter_pkg.vhd"
|
||||
vhdl work "../../src/fir_stage_pkg.vhd"
|
||||
vhdl work "../../src/fir_iterative_pkg.vhd"
|
||||
vhdl work "../../src/fir_stage.vhd"
|
||||
vhdl work "../../src/fir_iterative.vhd"
|
||||
vhdl work "../../src/syn_fir_iterative.vhd"
|
||||
@@ -0,0 +1,59 @@
|
||||
set -tmpdir "./xst/projnav.tmp"
|
||||
set -xsthdpdir "./xst"
|
||||
run
|
||||
-ifn syn_fir_iterative.prj
|
||||
-ifmt mixed
|
||||
-ofn syn_fir_iterative
|
||||
-ofmt NGC
|
||||
-p xc4vsx35-10-ff668
|
||||
-top syn_fir_iterative
|
||||
-opt_mode Speed
|
||||
-opt_level 1
|
||||
-power NO
|
||||
-iuc NO
|
||||
-lso syn_fir_iterative.lso
|
||||
-keep_hierarchy YES
|
||||
-rtlview Yes
|
||||
-glob_opt AllClockNets
|
||||
-read_cores YES
|
||||
-write_timing_constraints NO
|
||||
-cross_clock_analysis NO
|
||||
-hierarchy_separator /
|
||||
-bus_delimiter <>
|
||||
-case maintain
|
||||
-slice_utilization_ratio 100
|
||||
-bram_utilization_ratio 100
|
||||
-dsp_utilization_ratio 100
|
||||
-verilog2001 YES
|
||||
-fsm_extract YES -fsm_encoding Auto
|
||||
-safe_implementation No
|
||||
-fsm_style lut
|
||||
-ram_extract Yes
|
||||
-ram_style Auto
|
||||
-rom_extract Yes
|
||||
-mux_style Auto
|
||||
-decoder_extract YES
|
||||
-priority_extract YES
|
||||
-shreg_extract YES
|
||||
-shift_extract YES
|
||||
-xor_collapse YES
|
||||
-rom_style Auto
|
||||
-auto_bram_packing YES
|
||||
-mux_extract YES
|
||||
-resource_sharing YES
|
||||
-async_to_sync NO
|
||||
-use_dsp48 auto
|
||||
-iobuf YES
|
||||
-max_fanout 500
|
||||
-bufg 32
|
||||
-bufr 24
|
||||
-register_duplication YES
|
||||
-register_balancing No
|
||||
-slice_packing YES
|
||||
-optimize_primitives NO
|
||||
-use_clock_enable Auto
|
||||
-use_sync_set Auto
|
||||
-use_sync_reset Auto
|
||||
-iob auto
|
||||
-equivalent_register_removal YES
|
||||
-slice_utilization_ratio_maxmargin 5
|
||||
@@ -0,0 +1,7 @@
|
||||
vhdl work "W:\vhdl\lib\fixed\fixed_pkg_c.vhd"
|
||||
vhdl work "W:\vhdl\projects\radio\src\filter_pkg.vhd"
|
||||
vhdl work "W:\vhdl\projects\radio\src\fir_stage_pkg.vhd"
|
||||
vhdl work "W:\vhdl\projects\radio\src\fir_iterative_pkg.vhd"
|
||||
vhdl work "W:\vhdl\projects\radio\src\fir_stage.vhd"
|
||||
vhdl work "W:\vhdl\projects\radio\src\fir_iterative.vhd"
|
||||
vhdl work "W:\vhdl\projects\radio\src\syn_fir_iterative.vhd"
|
||||
@@ -0,0 +1,3 @@
|
||||
vhdl work "../../../../lib/src/fixed/fixed_pkg_c.vhd"
|
||||
vhdl work "../../src/mix_cpx_pkg.vhd"
|
||||
vhdl work "../../src/mix_cpx.vhd"
|
||||
@@ -0,0 +1,4 @@
|
||||
set -tmpdir "./xst/projnav.tmp"
|
||||
elaborate
|
||||
-ifn mix_cpx.prj
|
||||
-ifmt mixed
|
||||
@@ -0,0 +1,3 @@
|
||||
vhdl work "W:\vhdl\lib\src\fixed\fixed_pkg_c.vhd"
|
||||
vhdl work "W:\vhdl\projects\radio\src\mix_cpx_pkg.vhd"
|
||||
vhdl work "W:\vhdl\projects\radio\src\mix_cpx.vhd"
|
||||
@@ -0,0 +1 @@
|
||||
work
|
||||
@@ -0,0 +1,4 @@
|
||||
vhdl work "../../../../lib/src/fixed/fixed_pkg_c.vhd"
|
||||
vhdl work "../../src/mix_cpx_pkg.vhd"
|
||||
vhdl work "../../src/mix_cpx.vhd"
|
||||
vhdl work "../../src/syn_mix_cpx.vhd"
|
||||
@@ -0,0 +1,4 @@
|
||||
NET "sys_clk" TNM_NET = sys_clk;
|
||||
TIMESPEC TS_sys_clk = PERIOD "sys_clk" 5 ns;
|
||||
OFFSET = IN 8 ns BEFORE "sys_clk";
|
||||
OFFSET = OUT 12 ns AFTER "sys_clk";
|
||||
@@ -0,0 +1,59 @@
|
||||
set -tmpdir "./xst/projnav.tmp"
|
||||
set -xsthdpdir "./xst"
|
||||
run
|
||||
-ifn syn_mix_cpx.prj
|
||||
-ifmt mixed
|
||||
-ofn syn_mix_cpx
|
||||
-ofmt NGC
|
||||
-p xc4vsx35-10-ff668
|
||||
-top syn_mix_cpx
|
||||
-opt_mode Speed
|
||||
-opt_level 1
|
||||
-power NO
|
||||
-iuc NO
|
||||
-lso syn_mix_cpx.lso
|
||||
-keep_hierarchy NO
|
||||
-rtlview Yes
|
||||
-glob_opt AllClockNets
|
||||
-read_cores YES
|
||||
-write_timing_constraints NO
|
||||
-cross_clock_analysis NO
|
||||
-hierarchy_separator /
|
||||
-bus_delimiter <>
|
||||
-case maintain
|
||||
-slice_utilization_ratio 100
|
||||
-bram_utilization_ratio 100
|
||||
-dsp_utilization_ratio 100
|
||||
-verilog2001 YES
|
||||
-fsm_extract YES -fsm_encoding Auto
|
||||
-safe_implementation No
|
||||
-fsm_style lut
|
||||
-ram_extract Yes
|
||||
-ram_style Auto
|
||||
-rom_extract Yes
|
||||
-mux_style Auto
|
||||
-decoder_extract YES
|
||||
-priority_extract YES
|
||||
-shreg_extract YES
|
||||
-shift_extract YES
|
||||
-xor_collapse YES
|
||||
-rom_style Auto
|
||||
-auto_bram_packing NO
|
||||
-mux_extract YES
|
||||
-resource_sharing YES
|
||||
-async_to_sync NO
|
||||
-use_dsp48 auto
|
||||
-iobuf YES
|
||||
-max_fanout 500
|
||||
-bufg 32
|
||||
-bufr 24
|
||||
-register_duplication YES
|
||||
-register_balancing No
|
||||
-slice_packing YES
|
||||
-optimize_primitives NO
|
||||
-use_clock_enable Auto
|
||||
-use_sync_set Auto
|
||||
-use_sync_reset Auto
|
||||
-iob auto
|
||||
-equivalent_register_removal YES
|
||||
-slice_utilization_ratio_maxmargin 5
|
||||
@@ -0,0 +1,4 @@
|
||||
vhdl work "W:\vhdl\lib\src\fixed\fixed_pkg_c.vhd"
|
||||
vhdl work "W:\vhdl\projects\radio\src\mix_cpx_pkg.vhd"
|
||||
vhdl work "W:\vhdl\projects\radio\src\mix_cpx.vhd"
|
||||
vhdl work "W:\vhdl\projects\radio\src\syn_mix_cpx.vhd"
|
||||
@@ -0,0 +1,16 @@
|
||||
## NOTE: Do not edit this file.
|
||||
## Autogenerated by ProjNav (creatfdo.tcl) on Sat Jun 02 11:22:21 Westeuropäische Sommerzeit 2007
|
||||
##
|
||||
vlib work
|
||||
vcom -explicit -93 "../../../../lib/src/fixed/fixed_pkg_c.vhd"
|
||||
vcom -explicit -93 "../../src/mix_cpx_pkg.vhd"
|
||||
vcom -explicit -93 "../../src/mix_cpx.vhd"
|
||||
vcom -explicit -93 "../../src/syn_mix_cpx.vhd"
|
||||
vcom -explicit -93 "../../src/tb_syn_mix_cpx.vhd"
|
||||
vsim -t 1ps -lib work tb_syn_mix_cpx
|
||||
view wave
|
||||
add wave *
|
||||
do {tb_syn_mix_cpx.udo}
|
||||
view structure
|
||||
view signals
|
||||
run 1000ns
|
||||
@@ -0,0 +1,15 @@
|
||||
## NOTE: Do not edit this file.
|
||||
## Auto generated by Project Navigator for Post-Translate Simulation
|
||||
##
|
||||
vlib work
|
||||
## Compile Post-Translate Model
|
||||
vcom -explicit -93 "../../src/syn_mix_cpx.vhd"
|
||||
vcom -explicit -93 "../../src/tb_syn_mix_cpx.vhd"
|
||||
vsim -t 1ps -lib work tb_syn_mix_cpx
|
||||
do {tb_syn_mix_cpx.udo}
|
||||
view wave
|
||||
add wave *
|
||||
view structure
|
||||
view signals
|
||||
run 1000ns
|
||||
## End
|
||||
@@ -0,0 +1,15 @@
|
||||
## NOTE: Do not edit this file.
|
||||
## Auto generated by Project Navigator for Post-Translate Simulation
|
||||
##
|
||||
vlib work
|
||||
## Compile Post-Translate Model
|
||||
vcom -explicit -93 "./netgen/synthesis/syn_mix_cpx_synthesis.vhd"
|
||||
vcom -explicit -93 "../../src/tb_syn_mix_cpx.vhd"
|
||||
vsim -t 1ps -lib work tb_syn_mix_cpx
|
||||
do {tb_syn_mix_cpx.udo}
|
||||
view wave
|
||||
add wave *
|
||||
view structure
|
||||
view signals
|
||||
run 1000ns
|
||||
## End
|
||||
@@ -0,0 +1,4 @@
|
||||
-- ProjNav VHDL simulation template: tb_syn_mix_cpx.udo
|
||||
-- You may edit this file after the line that starts with
|
||||
-- '-- START' to customize your simulation
|
||||
-- START user-defined simulation commands
|
||||
@@ -0,0 +1 @@
|
||||
work
|
||||
@@ -0,0 +1,6 @@
|
||||
vhdl work "../../../../lib/fixed/fixed_pkg_c.vhd"
|
||||
vhdl work "../../../../lib/radio/nco/src/nco_pkg.vhd"
|
||||
vhdl work "../../../../lib/radio/nco/src/waverom_dual.vhd"
|
||||
vhdl work "../../../../lib/radio/nco/src/wavelut.vhd"
|
||||
vhdl work "../../../../lib/radio/nco/src/nco.vhd"
|
||||
vhdl work "../../src/syn_nco.vhd"
|
||||
@@ -0,0 +1,4 @@
|
||||
NET "clk" TNM_NET = clk;
|
||||
TIMESPEC TS_clk = PERIOD "clk" 10 ns;
|
||||
OFFSET = IN 8 ns BEFORE "clk";
|
||||
OFFSET = OUT 12 ns AFTER "clk";
|
||||
@@ -0,0 +1,59 @@
|
||||
set -tmpdir "./xst/projnav.tmp"
|
||||
set -xsthdpdir "./xst"
|
||||
run
|
||||
-ifn syn_nco.prj
|
||||
-ifmt mixed
|
||||
-ofn syn_nco
|
||||
-ofmt NGC
|
||||
-p xc4vsx35-10-ff668
|
||||
-top syn_nco
|
||||
-opt_mode Speed
|
||||
-opt_level 1
|
||||
-power NO
|
||||
-iuc NO
|
||||
-lso syn_nco.lso
|
||||
-keep_hierarchy YES
|
||||
-rtlview Yes
|
||||
-glob_opt AllClockNets
|
||||
-read_cores YES
|
||||
-write_timing_constraints NO
|
||||
-cross_clock_analysis NO
|
||||
-hierarchy_separator /
|
||||
-bus_delimiter <>
|
||||
-case maintain
|
||||
-slice_utilization_ratio 100
|
||||
-bram_utilization_ratio 100
|
||||
-dsp_utilization_ratio 100
|
||||
-verilog2001 YES
|
||||
-fsm_extract YES -fsm_encoding Auto
|
||||
-safe_implementation No
|
||||
-fsm_style lut
|
||||
-ram_extract Yes
|
||||
-ram_style Auto
|
||||
-rom_extract Yes
|
||||
-mux_style Auto
|
||||
-decoder_extract YES
|
||||
-priority_extract YES
|
||||
-shreg_extract YES
|
||||
-shift_extract YES
|
||||
-xor_collapse YES
|
||||
-rom_style Auto
|
||||
-auto_bram_packing YES
|
||||
-mux_extract YES
|
||||
-resource_sharing YES
|
||||
-async_to_sync NO
|
||||
-use_dsp48 auto
|
||||
-iobuf YES
|
||||
-max_fanout 500
|
||||
-bufg 32
|
||||
-bufr 24
|
||||
-register_duplication YES
|
||||
-register_balancing No
|
||||
-slice_packing YES
|
||||
-optimize_primitives NO
|
||||
-use_clock_enable Auto
|
||||
-use_sync_set Auto
|
||||
-use_sync_reset Auto
|
||||
-iob auto
|
||||
-equivalent_register_removal YES
|
||||
-slice_utilization_ratio_maxmargin 5
|
||||
@@ -0,0 +1,6 @@
|
||||
vhdl work "W:\vhdl\lib\fixed\fixed_pkg_c.vhd"
|
||||
vhdl work "W:\vhdl\lib\radio\nco\src\nco_pkg.vhd"
|
||||
vhdl work "W:\vhdl\lib\radio\nco\src\waverom_dual.vhd"
|
||||
vhdl work "W:\vhdl\lib\radio\nco\src\wavelut.vhd"
|
||||
vhdl work "W:\vhdl\lib\radio\nco\src\nco.vhd"
|
||||
vhdl work "W:\vhdl\projects\radio\src\syn_nco.vhd"
|
||||
Reference in New Issue
Block a user