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- removed 'reg_rd' which is fed into pipeline.

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if cop is read is now implemented into instruction decoder
- simplified use of stall signals
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git-svn-id: http://moon:8086/svn/vhdl/trunk@398 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2009-03-17 09:35:39 +00:00
parent e2c40b91a1
commit 4bf6b28c71
1 changed files with 4 additions and 7 deletions
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lib/CPUs/MIPS/src/core/mips_cop.vhd
+4 -7
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@@ -44,7 +44,6 @@ entity cop is
ir : in word_t; ir : in word_t;
ctrl_in : in cop0_ctrl_in_t; ctrl_in : in cop0_ctrl_in_t;
ctrl_out : out cop0_ctrl_out_t; ctrl_out : out cop0_ctrl_out_t;
reg_rd : out STD_LOGIC;
din : in word_t; din : in word_t;
dout : out word_t dout : out word_t
); );
@@ -120,8 +119,6 @@ begin
ctrl_out.user_mode <= status(1); ctrl_out.user_mode <= status(1);
ctrl_out.int <= eflags.Int; ctrl_out.int <= eflags.Int;
reg_rd <= cop_pipe_ID.cs and cop_pipe_ID.re after 1 ns;
im <= status(15 downto 8); im <= status(15 downto 8);
cause <= bd & (30 downto 16 => '0') & ip & '0' & exc_code & "00"; cause <= bd & (30 downto 16 => '0') & ip & '0' & exc_code & "00";
@@ -175,13 +172,13 @@ exception_state:
when exc_commit_EX => when exc_commit_EX =>
ctrl_out.exc_pending <= '1'; ctrl_out.exc_pending <= '1';
ctrl_out.exc_commit <= '1'; ctrl_out.exc_commit <= '1';
if ctrl_in.sdu.EX_stall = '0' then if ctrl_in.sdu.stall_all = '0' then
exc_staten <= exc_commit_MEM; exc_staten <= exc_commit_MEM;
end if; end if;
when exc_commit_MEM => when exc_commit_MEM =>
ctrl_out.exc_pending <= '1'; ctrl_out.exc_pending <= '1';
if ctrl_in.sdu.MEM_stall = '0' then if ctrl_in.sdu.stall_all = '0' then
epc_reg_we <= '1'; epc_reg_we <= '1';
exc_staten <= exc_idle; exc_staten <= exc_idle;
end if; end if;
@@ -311,7 +308,7 @@ cop_pipe:
cop_pipe_EX.we <= '0'; cop_pipe_EX.we <= '0';
cop_pipe_EX.re <= '0'; cop_pipe_EX.re <= '0';
else else
if ctrl_in.sdu.EX_stall = '0' then if ctrl_in.sdu.stall_all = '0' then
cop_pipe_EX <= cop_pipe_ID; cop_pipe_EX <= cop_pipe_ID;
end if; end if;
end if; end if;
@@ -322,7 +319,7 @@ cop_register_read:
process(clk) process(clk)
variable reg : word_t; variable reg : word_t;
begin begin
if rising_edge(clk) and cop_pipe_ID.re = '1' and ctrl_in.sdu.ID_stall = '0' then if rising_edge(clk) and cop_pipe_ID.re = '1' and ctrl_in.sdu.stall_all = '0' then
case cop_pipe_ID.rd is case cop_pipe_ID.rd is
when "01000" => -- BadVAddr when "01000" => -- BadVAddr
reg := BadVAddr; reg := BadVAddr;