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- integrated ITLB and DTLB into pipeline.

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TLB queries come from pipeline if generic PIPE_ITLB or  PIPE_DTLB is true. Cache query is then disabled.
  If generic PIPE_ITLB or  PIPE_DTLB set to false queries come from cache.
  Piped TLB queries are piped translations with latency of two clocks. Piped translation allow physically indexed and physically tagged caches
- reworked PC logic
- prepared for individual BCUs in EX, MEM and WB stage
- changed LTS and LTU generation in ALU

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git-svn-id: http://moon:8086/svn/vhdl/branches/BRANCH_MIPS_TLB@1016 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2013-08-18 19:03:43 +00:00
parent 81698e2391
commit 4ba64fdb3b
1 changed files with 5 additions and 1 deletions
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lib/CPUs/MIPS/src/tb_mips_top.vhd
+5 -1
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@@ -43,6 +43,8 @@ ARCHITECTURE behavior OF tb_mips_top IS
constant SRAM_ADDR_WIDTH : integer := 17; -- bits constant SRAM_ADDR_WIDTH : integer := 17; -- bits
constant FLASH_ADDR_WIDTH : integer := 17; -- bits constant FLASH_ADDR_WIDTH : integer := 17; -- bits
constant WITH_TLB : boolean := true; constant WITH_TLB : boolean := true;
constant ITLB_PIPE : boolean := true;
constant DTLB_PIPE : boolean := true;
constant KSEG_01_TRANSLATED : boolean := true; constant KSEG_01_TRANSLATED : boolean := true;
signal debug : chip_debug_t; signal debug : chip_debug_t;
signal tb_fin : STD_LOGIC := '0'; signal tb_fin : STD_LOGIC := '0';
@@ -281,7 +283,9 @@ uut: entity work.mips_top
( (
icache_size => 256, -- words icache_size => 256, -- words
dcache_size => 256, -- words dcache_size => 256, -- words
WITH_TLB => WITH_TLB WITH_TLB => WITH_TLB,
ITLB_PIPE => ITLB_PIPE,
DTLB_PIPE => DTLB_PIPE
) )
PORT MAP PORT MAP
( (