From 4ba64fdb3b098a03515aa2651a44f3f6f8c8fb48 Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Sun, 18 Aug 2013 19:03:43 +0000 Subject: [PATCH] - integrated ITLB and DTLB into pipeline. TLB queries come from pipeline if generic PIPE_ITLB or PIPE_DTLB is true. Cache query is then disabled. If generic PIPE_ITLB or PIPE_DTLB set to false queries come from cache. Piped TLB queries are piped translations with latency of two clocks. Piped translation allow physically indexed and physically tagged caches - reworked PC logic - prepared for individual BCUs in EX, MEM and WB stage - changed LTS and LTU generation in ALU Committed on the Free edition of March Hare Software CVSNT Server. Upgrade to CVS Suite for more features and support: http://march-hare.com/cvsnt/ git-svn-id: http://moon:8086/svn/vhdl/branches/BRANCH_MIPS_TLB@1016 cc03376c-175c-47c8-b038-4cd826a8556b --- lib/CPUs/MIPS/src/tb_mips_top.vhd | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/lib/CPUs/MIPS/src/tb_mips_top.vhd b/lib/CPUs/MIPS/src/tb_mips_top.vhd index 1cfc94a..7e9a88c 100644 --- a/lib/CPUs/MIPS/src/tb_mips_top.vhd +++ b/lib/CPUs/MIPS/src/tb_mips_top.vhd @@ -43,6 +43,8 @@ ARCHITECTURE behavior OF tb_mips_top IS constant SRAM_ADDR_WIDTH : integer := 17; -- bits constant FLASH_ADDR_WIDTH : integer := 17; -- bits constant WITH_TLB : boolean := true; + constant ITLB_PIPE : boolean := true; + constant DTLB_PIPE : boolean := true; constant KSEG_01_TRANSLATED : boolean := true; signal debug : chip_debug_t; signal tb_fin : STD_LOGIC := '0'; @@ -281,7 +283,9 @@ uut: entity work.mips_top ( icache_size => 256, -- words dcache_size => 256, -- words - WITH_TLB => WITH_TLB + WITH_TLB => WITH_TLB, + ITLB_PIPE => ITLB_PIPE, + DTLB_PIPE => DTLB_PIPE ) PORT MAP (