diff --git a/lib/CPUs/MIPS/src/tb_mips_top.vhd b/lib/CPUs/MIPS/src/tb_mips_top.vhd
index 1cfc94a..7e9a88c 100644
--- a/lib/CPUs/MIPS/src/tb_mips_top.vhd
+++ b/lib/CPUs/MIPS/src/tb_mips_top.vhd
@@ -43,6 +43,8 @@ ARCHITECTURE behavior OF tb_mips_top IS
 	constant SRAM_ADDR_WIDTH		: integer := 17;		-- bits
 	constant FLASH_ADDR_WIDTH		: integer := 17;		-- bits
 	constant WITH_TLB				: boolean := true;
+	constant ITLB_PIPE				: boolean := true;
+	constant DTLB_PIPE				: boolean := true;
 	constant KSEG_01_TRANSLATED		: boolean := true;
 	signal debug					: chip_debug_t;
 	signal tb_fin					: STD_LOGIC := '0';
@@ -281,7 +283,9 @@ uut: entity work.mips_top
 	(
 		icache_size		=> 256,		-- words
 		dcache_size		=> 256,		-- words
-		WITH_TLB		=> WITH_TLB
+		WITH_TLB		=> WITH_TLB,
+		ITLB_PIPE		=> ITLB_PIPE,
+		DTLB_PIPE		=> DTLB_PIPE
 	)
 	PORT MAP
 	(