[DE0-Nano]
- added dip switches git-svn-id: http://moon:8086/svn/vhdl/trunk@1379 cc03376c-175c-47c8-b038-4cd826a8556b
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@@ -311,4 +311,8 @@ set_global_assignment -name VHDL_FILE ../../../../../repos/lib/CPUs/MIPS/src/cor
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set_global_assignment -name VHDL_FILE ../../../../../repos/lib/CPUs/MIPS/src/core/mips_alu.vhd
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set_global_assignment -name VHDL_FILE mips_sys.vhd
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set_global_assignment -name VHDL_FILE ../../../../../repos/lib/misc/jtag_reg_alt.vhd
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set_location_assignment PIN_M1 -to dip_sw[0]
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set_location_assignment PIN_T8 -to dip_sw[1]
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set_location_assignment PIN_B9 -to dip_sw[2]
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set_location_assignment PIN_M15 -to dip_sw[3]
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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@@ -62,7 +62,7 @@ ENTITY mips_sys IS
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uart_rx : in unsigned(1 downto 0);
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uart_tx : out unsigned(1 downto 0);
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dip_sw : in unsigned(3 downto 0);
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sys_leds : out unsigned(7 downto 0)
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);
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END mips_sys;
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@@ -138,9 +138,10 @@ ARCHITECTURE behavior OF mips_sys IS
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signal sys_rst_count : unsigned(7 downto 0) := (others => '1'); -- pre-init for POR
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BEGIN
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sys_nmi <= not sys_nmi_n;
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sys_leds <= cpu_debug & gpo0(5 downto 0);
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spi_ss_n <= not spi_ss;
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sys_nmi <= not sys_nmi_n;
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sys_leds <= cpu_debug & gpo0(5 downto 0);
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spi_ss_n <= not spi_ss;
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gpi0(11 downto 8) <= dip_sw;
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sys_reset:
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process(sys_clk)
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