jens
46e8e2d093
- added dip switches git-svn-id: http://moon:8086/svn/vhdl/trunk@1379 cc03376c-175c-47c8-b038-4cd826a8556b
442 lines
11 KiB
VHDL
442 lines
11 KiB
VHDL
-------------------------------------------------------------------------
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-- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
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-- This file: Testbench for JCPU
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-- also writes 'opc.lst' for JASM-assembler
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--
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-- Copyright (C) 2007 J. Ahrensfeld
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--
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-- This program is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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--
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-- For questions and ideas, please contact the author at jens@jayfield.org
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--
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--------------------------------------------------------------------------
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LIBRARY ieee;
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use IEEE.STD_LOGIC_1164.ALL;
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USE ieee.numeric_std.ALL;
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library work;
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use work.mips_types.all;
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use work.sdram_types.all;
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use work.sdram_config.all;
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ENTITY mips_sys IS
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GENERIC
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(
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ICACHE_SIZE : natural := 4096; -- words
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DCACHE_SIZE : natural := 4096; -- words
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F_SYSCLK : real := 50.0
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);
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PORT
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(
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sys_nmi_n : in std_logic;
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sys_rst_n : in std_logic;
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sys_clk : in std_logic;
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-- SDRAM signals
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sys_sdram_clk : out STD_LOGIC;
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sys_sdram_cke : out STD_LOGIC;
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sys_sdram_cs_n : out STD_LOGIC;
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sys_sdram_cas_n : out STD_LOGIC;
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sys_sdram_ras_n : out STD_LOGIC;
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sys_sdram_we_n : out STD_LOGIC;
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sys_sdram_addr : out sdr_addr_t;
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sys_sdram_ba : out sdr_ba_t;
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sys_sdram_dqm : out unsigned(PART_DM_WIDTH-1 downto 0);
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sys_sdram_data : inout unsigned(PART_DATA_WIDTH-1 downto 0);
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spi_ss_n : out std_logic;
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spi_clk : out std_logic;
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spi_miso : in std_logic;
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spi_mosi : out std_logic;
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uart_rx : in unsigned(1 downto 0);
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uart_tx : out unsigned(1 downto 0);
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dip_sw : in unsigned(3 downto 0);
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sys_leds : out unsigned(7 downto 0)
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);
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END mips_sys;
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ARCHITECTURE behavior OF mips_sys IS
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signal cpu_debug : unsigned(1 downto 0);
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signal INT : unsigned (5 downto 0) := (others => '0');
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-- J-BUS Master
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signal ACK_I : STD_LOGIC;
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signal SRDY_I : STD_LOGIC;
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signal ADDR_O : unsigned(31 downto 0);
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signal DAT_I : unsigned(31 downto 0);
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signal DAT_O : unsigned(31 downto 0);
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signal WE_O : STD_LOGIC;
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signal SEL_O : unsigned(3 downto 0);
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signal CYC_O : STD_LOGIC;
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signal STB_O : STD_LOGIC;
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signal MRDY_O : STD_LOGIC;
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-- J-BUS Slaves
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signal CYC_I_rom : std_logic;
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signal ACK_O_rom : std_logic;
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signal SRDY_O_rom : std_logic;
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signal DAT_O_rom : unsigned(31 downto 0);
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signal CYC_I_ram : std_logic;
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signal ACK_O_ram : std_logic;
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signal SRDY_O_ram : std_logic;
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signal DAT_O_ram : unsigned(31 downto 0);
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signal CYC_I_gpio : std_logic;
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signal ACK_O_gpio : std_logic;
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signal SRDY_O_gpio : std_logic;
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signal DAT_O_gpio : unsigned(31 downto 0);
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signal CYC_I_uart0 : std_logic;
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signal ACK_O_uart0 : std_logic;
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signal SRDY_O_uart0 : std_logic;
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signal DAT_O_uart0 : unsigned(31 downto 0);
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signal CYC_I_uart1 : std_logic;
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signal ACK_O_uart1 : std_logic;
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signal SRDY_O_uart1 : std_logic;
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signal DAT_O_uart1 : unsigned(31 downto 0);
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signal CYC_I_flash : std_logic;
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signal ACK_O_flash : std_logic;
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signal SRDY_O_flash : std_logic;
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signal DAT_O_flash : unsigned(31 downto 0);
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signal spi_ss : std_LOGIC;
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signal cpu_tx_data : unsigned(7 downto 0);
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signal cpu_tx_data_vld : std_logic;
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signal int_timer : std_logic;
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signal int_uart0 : std_logic;
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signal int_uart1 : std_logic;
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signal int_flash : std_logic;
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type mem_area_t is (mem_dead, mem_flash, mem_ram, mem_rom, mem_gpio, mem_uart0, mem_uart1);
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signal mem_area : mem_area_t;
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signal gpo0 : unsigned(31 downto 0);
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signal gpi0 : unsigned(31 downto 0) := (others => '0');
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signal sys_nmi : STD_LOGIC;
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signal cpu_rst : STD_LOGIC := '1'; -- pre-init for POR
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signal sys_rst : STD_LOGIC := '1'; -- pre-init for POR
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signal cpu_rst_count : unsigned(24 downto 0) := (others => '1'); -- pre-init for POR
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signal sys_rst_count : unsigned(7 downto 0) := (others => '1'); -- pre-init for POR
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BEGIN
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sys_nmi <= not sys_nmi_n;
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sys_leds <= cpu_debug & gpo0(5 downto 0);
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spi_ss_n <= not spi_ss;
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gpi0(11 downto 8) <= dip_sw;
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sys_reset:
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process(sys_clk)
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begin
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if rising_edge(sys_clk) then
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if sys_rst_n = '0' then
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sys_rst <= '1';
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sys_rst_count <= (others => '1');
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elsif (sys_rst_count /= 0) then
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sys_rst_count <= sys_rst_count - 1;
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else
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sys_rst <= '0';
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end if;
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end if;
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end process;
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cpu_reset:
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process(sys_clk)
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begin
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if rising_edge(sys_clk) then
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if sys_rst_n = '0' then
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cpu_rst <= '1';
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cpu_rst_count <= (others => '1');
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elsif (cpu_rst_count /= 0) then
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cpu_rst_count <= cpu_rst_count - 1;
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else
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cpu_rst <= '0';
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end if;
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end if;
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end process;
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------------------------------------------------------------------
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-- Memory mux
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------------------------------------------------------------------
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mem_mux:
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process(ADDR_O)
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begin
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mem_area <= mem_dead;
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if ADDR_O(31 downto 28) = X"0" then
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mem_area <= mem_flash;
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elsif ADDR_O(31 downto 28) = X"A" then
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if ADDR_O(27 downto 26) = "00" then
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if ADDR_O(18 downto 16) = "000" then
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mem_area <= mem_gpio;
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elsif ADDR_O(18 downto 16) = "001" then
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mem_area <= mem_uart0;
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elsif ADDR_O(18 downto 16) = "011" then
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mem_area <= mem_uart1;
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end if;
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elsif ADDR_O(27 downto 26) = "01" then
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mem_area <= mem_flash;
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end if;
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elsif (ADDR_O(31 downto 28) = X"B" and ADDR_O(15) = '0') then
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mem_area <= mem_rom;
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elsif (ADDR_O(31 downto 28) = X"8" or ADDR_O(30) = '1') then
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mem_area <= mem_ram;
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end if;
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end process;
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signal_mux:
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process(mem_area, CYC_O)
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begin
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CYC_I_gpio <= '0';
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CYC_I_uart0 <= '0';
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CYC_I_uart1 <= '0';
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CYC_I_flash <= '0';
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CYC_I_rom <= '0';
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CYC_I_ram <= '0';
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case mem_area is
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when mem_gpio =>
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CYC_I_gpio <= CYC_O;
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when mem_uart0 =>
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CYC_I_uart0 <= CYC_O;
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when mem_uart1 =>
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CYC_I_uart1 <= CYC_O;
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when mem_flash =>
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CYC_I_flash <= CYC_O;
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when mem_rom =>
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CYC_I_rom <= CYC_O;
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when mem_ram =>
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CYC_I_ram <= CYC_O;
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when others => null;
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end case;
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end process;
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SRDY_I <= SRDY_O_ram or SRDY_O_rom or SRDY_O_uart0 or SRDY_O_uart1 or SRDY_O_flash or SRDY_O_gpio;
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ACK_I <= ACK_O_ram or ACK_O_rom or ACK_O_uart0 or ACK_O_uart1 or ACK_O_flash or ACK_O_gpio;
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DAT_I <= DAT_O_ram when CYC_I_ram = '1' else
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DAT_O_rom when CYC_I_rom = '1' else
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DAT_O_uart0 when CYC_I_uart0 = '1' else
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DAT_O_uart1 when CYC_I_uart1 = '1' else
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DAT_O_flash when CYC_I_flash = '1' else
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DAT_O_gpio when CYC_I_gpio = '1' else X"DEADBEEF";
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------------------------------------------------------------------
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inst_mips_top: entity work.mips_top
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GENERIC MAP
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(
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icache_size => ICACHE_SIZE, -- words
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dcache_size => DCACHE_SIZE -- words
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)
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PORT MAP
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(
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debug => cpu_debug,
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nmi => sys_nmi,
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eb => '1',
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cpu_clk => sys_clk,
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RST_I => cpu_rst,
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CLK_I => sys_clk,
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ACK_I => ACK_I,
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SRDY_I => SRDY_I,
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ADDR_O => ADDR_O,
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DAT_I => DAT_I,
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DAT_O => DAT_O,
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WE_O => WE_O,
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SEL_O => SEL_O,
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CYC_O => CYC_O,
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STB_O => STB_O,
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MRDY_O => MRDY_O,
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INT => INT
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);
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INT <= "00" & int_flash & int_uart1 & int_uart0 & int_timer;
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inst_rom : entity work.rom_wb
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PORT MAP
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(
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CLK_I => sys_clk,
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RST_I => sys_rst,
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CYC_I => CYC_I_rom,
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STB_I => STB_O,
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WE_I => WE_O,
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ACK_O => ACK_O_rom,
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MRDY_I => MRDY_O,
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SRDY_O => SRDY_O_rom,
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ADDR_I => ADDR_O,
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DAT_O => DAT_O_rom
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);
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inst_gpio : entity work.gpio_wb
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GENERIC MAP
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(
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f_sysclk => F_SYSCLK
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)
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PORT MAP
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(
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CLK_I => sys_clk,
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RST_I => sys_rst,
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CYC_I => CYC_I_gpio,
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STB_I => STB_O,
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SEL_I => SEL_O,
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WE_I => WE_O,
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ACK_O => ACK_O_gpio,
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SRDY_O => SRDY_O_gpio,
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MRDY_I => MRDY_O,
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ADDR_I => ADDR_O,
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DAT_I => DAT_O,
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DAT_O => DAT_O_gpio,
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INT_TIM_O => int_timer,
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sys_gpi_0 => gpi0,
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sys_gpo_0 => gpo0
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);
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inst_uart0 : entity work.uart_wb
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GENERIC MAP
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(
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f_sysclk => F_SYSCLK,
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baudrate_default => 460800.0,
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fifo_depth_bits => 4
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)
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PORT MAP
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(
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CLK_I => sys_clk,
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RST_I => sys_rst,
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CYC_I => CYC_I_uart0,
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STB_I => STB_O,
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SEL_I => SEL_O,
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WE_I => WE_O,
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ACK_O => ACK_O_uart0,
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SRDY_O => SRDY_O_uart0,
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MRDY_I => MRDY_O,
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ADDR_I => ADDR_O,
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DAT_I => DAT_O,
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DAT_O => DAT_O_uart0,
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INT_O => int_uart0,
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ser_rx => uart_rx(0),
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ser_tx => uart_tx(0)
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);
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inst_uart1 : entity work.uart_wb
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GENERIC MAP
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(
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f_sysclk => F_SYSCLK,
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baudrate_default => 460800.0,
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fifo_depth_bits => 4
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)
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PORT MAP
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(
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CLK_I => sys_clk,
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RST_I => sys_rst,
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CYC_I => CYC_I_uart1,
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STB_I => STB_O,
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SEL_I => SEL_O,
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WE_I => WE_O,
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ACK_O => ACK_O_uart1,
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SRDY_O => SRDY_O_uart1,
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MRDY_I => MRDY_O,
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ADDR_I => ADDR_O,
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DAT_I => DAT_O,
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DAT_O => DAT_O_uart1,
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INT_O => int_uart1,
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ser_rx => uart_rx(1),
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ser_tx => uart_tx(1)
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);
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inst_spi_flash : entity work.spi_flash_wb
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GENERIC MAP
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(
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FLASH_ADDR_BITS => 24,
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CACHE_ADDR_BITS => 8
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)
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PORT MAP
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(
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CLK_I => sys_clk,
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RST_I => sys_rst,
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CYC_I => CYC_I_flash,
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STB_I => STB_O,
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SEL_I => SEL_O,
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WE_I => WE_O,
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ACK_O => ACK_O_flash,
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SRDY_O => SRDY_O_flash,
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MRDY_I => MRDY_O,
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ADDR_I => ADDR_O,
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DAT_I => DAT_O,
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DAT_O => DAT_O_flash,
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INT_O => int_flash,
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spi_hold => '0',
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spi_ss => spi_ss,
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spi_clk => spi_clk,
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spi_miso => spi_miso,
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spi_mosi => spi_mosi
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);
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-- DDR SDRAM Controller Core
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inst_ctrl_sdr_wb32 : entity work.ctrl_sdr_wb32
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GENERIC MAP
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(
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F_SYSCLK => F_SYSCLK,
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F_SDRCLK_IN => F_SYSCLK,
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F_SDRCLK => 100.000,
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FIFO_DEPTH => 4,
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TPD_BOARD_SIM => 3100 ps
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)
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PORT MAP
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(
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RST_I => sys_rst,
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CLK_I => sys_clk,
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SDRAM_CLK_I => sys_clk,
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SDRAM_CLK_FB_I => sys_clk,
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CYC_I => CYC_I_ram,
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STB_I => STB_O,
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SEL_I => SEL_O,
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WE_I => WE_O,
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ACK_O => ACK_O_ram,
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SRDY_O => SRDY_O_ram,
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MRDY_I => MRDY_O,
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ADDR_I => ADDR_O,
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DAT_I => DAT_O,
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DAT_O => DAT_O_ram,
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-- SDRAM signals
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sd_clk => sys_sdram_clk,
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sd_cke => sys_sdram_cke,
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sd_cs_n => sys_sdram_cs_n,
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sd_cas_n => sys_sdram_cas_n,
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sd_ras_n => sys_sdram_ras_n,
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sd_we_n => sys_sdram_we_n,
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sd_addr => sys_sdram_addr,
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sd_ba => sys_sdram_ba,
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sd_dqm => sys_sdram_dqm,
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sd_data => sys_sdram_data
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);
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END;
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