From 3685973be870a0b1b97bd24654cda1738b301245 Mon Sep 17 00:00:00 2001
From: Jens Ahrensfeld <jens@jayfield.org>
Date: Sat, 18 Oct 2008 11:37:01 +0000
Subject: [PATCH] - using now 64-bit SDR interface (2 SDRAMS)

git-svn-id: http://moon:8086/svn/vhdl/trunk@72 cc03376c-175c-47c8-b038-4cd826a8556b
---
 lib/SDRAM/ddr_sdr_v1_5/src/sdram_config.vhd   |   2 +-
 .../src/tb_sdram_ctrl_frontend_wb.vhd         | 856 ++++++++++++------
 2 files changed, 603 insertions(+), 255 deletions(-)

diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_config.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_config.vhd
index b62e085..b0a6253 100644
--- a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_config.vhd
+++ b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_config.vhd
@@ -27,7 +27,7 @@ USE IEEE.NUMERIC_STD.ALL;
 
 package sdram_config is
 
-	constant DDR_DATA_WIDTH 	: positive := 16;  -- External DDR-SDRAM Module data bus width
+	constant DDR_DATA_WIDTH 	: positive := 32;  -- External DDR-SDRAM Module data bus width
 	constant DDR_ADDR_WIDTH 	: positive := 13;  -- number of address lines to DDR-SDRAM Device/Module
 	constant DDR_BANK_WIDTH 	: positive := 2;   -- Number of BANK address lines of external DDR-SDRAM
 	constant DDR_ROW_ADDR_WIDTH	: positive := 13;  -- 
diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/tb_sdram_ctrl_frontend_wb.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/tb_sdram_ctrl_frontend_wb.vhd
index 1357c98..2fd94e7 100644
--- a/lib/SDRAM/ddr_sdr_v1_5/src/tb_sdram_ctrl_frontend_wb.vhd
+++ b/lib/SDRAM/ddr_sdr_v1_5/src/tb_sdram_ctrl_frontend_wb.vhd
@@ -76,8 +76,43 @@ architecture struct of tb_sdram_ctrl_frontend_wb is
 	signal dout_reg			: unsigned(31 downto 0);
 	signal dout_cnt			: natural range 0 to 255;
 
+	type sd_cmd_t is (nop, lmr, ar, pre, act, write, read, bst);
+	signal sd_cmd : sd_cmd_t;
+	
 begin 
    
+	process(part_cs_n, part_ras_n, part_cas_n, part_we_n)
+	variable cmd : unsigned (2 downto 0);
+
+	begin
+		cmd := part_ras_n & part_cas_n & part_we_n;
+		sd_cmd <= nop;
+		if part_cs_n = '0' then
+			case cmd is
+				when "000" =>
+					sd_cmd <= lmr;
+				when "001" =>
+					sd_cmd <= ar;
+				when "010" =>
+					sd_cmd <= pre;
+				when "011" =>
+					sd_cmd <= act;
+				when "100" =>
+					sd_cmd <= write;
+				when "101" =>
+					sd_cmd <= read;
+				when "110" =>
+					sd_cmd <= bst;
+				when "111" =>
+					sd_cmd <= nop;
+				
+				when others =>
+					sd_cmd <= nop;
+
+			end case;
+		end if;
+	end process;
+	
 inst_clockgen : entity work.clockgen
 	GENERIC MAP
 	(
@@ -144,13 +179,12 @@ inst_clockgen : entity work.clockgen
 		
 	);
    
-
    -- MICRON DDR SDRAM Simulation Model
 i_mt46v16m16_0 : entity work.mt46v16m16 
       port map
       (
-         dq    => std_logic_vector(part_data),
-         dqs   => std_logic_vector(part_dqs),
+         dq    => std_logic_vector(part_data(15 downto 0)),
+         dqs   => std_logic_vector(part_dqs(1 downto 0)),
          addr  => std_logic_vector(part_addr),
          ba    => std_logic_vector(part_ba),
          clk   => part_clk_p,
@@ -160,7 +194,25 @@ i_mt46v16m16_0 : entity work.mt46v16m16
          ras_n => part_ras_n,
          cas_n => part_cas_n,
          we_n  => part_we_n,
-         dm    => std_logic_vector(part_dm)
+         dm    => std_logic_vector(part_dm(1 downto 0))
+	);
+
+   -- MICRON DDR SDRAM Simulation Model
+i_mt46v16m16_1 : entity work.mt46v16m16 
+      port map
+      (
+         dq    => std_logic_vector(part_data(31 downto 16)),
+         dqs   => std_logic_vector(part_dqs(3 downto 2)),
+         addr  => std_logic_vector(part_addr),
+         ba    => std_logic_vector(part_ba),
+         clk   => part_clk_p,
+         clk_n => part_clk_n,
+         cke   => part_cke,
+         cs_n  => part_cs_n,
+         ras_n => part_ras_n,
+         cas_n => part_cas_n,
+         we_n  => part_we_n,
+         dm    => std_logic_vector(part_dm(3 downto 2))
 	);
 
 CLK_GEN: process
@@ -198,125 +250,22 @@ STIMULUS: process
 		WE_O	<= '1';
 		DAT_O	<= X"1234_0000";
 		ADDR_O	<= X"0000_0000";
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		DAT_O	<= DAT_O + 1;
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		DAT_O	<= DAT_O + 1;
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		DAT_O	<= DAT_O + 1;
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		DAT_O	<= DAT_O + 1;
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		DAT_O	<= DAT_O + 1;
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		DAT_O	<= DAT_O + 1;
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		DAT_O	<= DAT_O + 1;
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		DAT_O	<= DAT_O + 1;
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		DAT_O	<= DAT_O + 1;
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		DAT_O	<= DAT_O + 1;
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		DAT_O	<= DAT_O + 1;
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		DAT_O	<= DAT_O + 1;
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		DAT_O	<= DAT_O + 1;
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		DAT_O	<= DAT_O + 1;
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		DAT_O	<= DAT_O + 1;
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		DAT_O	<= DAT_O + 1;
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		DAT_O	<= DAT_O + 1;
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		DAT_O	<= DAT_O + 1;
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		DAT_O	<= DAT_O + 1;
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		DAT_O	<= DAT_O + 1;
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		DAT_O	<= DAT_O + 1;
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		DAT_O	<= DAT_O + 1;
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		DAT_O	<= DAT_O + 1;
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		DAT_O	<= DAT_O + 1;
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		DAT_O	<= DAT_O + 1;
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		DAT_O	<= DAT_O + 1;
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		DAT_O	<= DAT_O + 1;
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		DAT_O	<= DAT_O + 1;
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		DAT_O	<= DAT_O + 1;
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		DAT_O	<= DAT_O + 1;
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		DAT_O	<= DAT_O + 1;
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		DAT_O	<= DAT_O + 1;
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		DAT_O	<= DAT_O + 1;
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		DAT_O	<= DAT_O + 1;
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		DAT_O	<= DAT_O + 1;
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		DAT_O	<= DAT_O + 1;
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		DAT_O	<= DAT_O + 1;
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		
+		for i in 0 to 8192 loop
+			wait until rising_edge(CLK_O) and SRDY_I = '1';
+			DAT_O	<= DAT_O + 1;
+			ADDR_O	<= ADDR_O + 4;
+		end loop;
+	
 		STB_O	<= '0';
-		wait until rising_edge(CLK_O) and ACK_I = '1';
+		wait until rising_edge(CLK_O);
 		CYC_O	<= '0';
 
-		
-		-- 8-word burst cycle
+		------------------------------------------------------------
 		wait for 3*CLK_PERIOD;
+		------------------------------------------------------------
+
+		-- 8-word burst cycle
 		dout_rst	<= '1';
 		wait until rising_edge(CLK_O);
 		dout_rst	<= '0';
@@ -324,27 +273,21 @@ STIMULUS: process
 		STB_O	<= '1';
 		WE_O	<= '0';
 		ADDR_O	<= X"0000_0000";
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		STB_O	<= '0';
+
+		for i in 0 to 31 loop
+			wait until rising_edge(CLK_O) and SRDY_I = '1';
+			DAT_O	<= DAT_O + 1;
+			ADDR_O	<= ADDR_O + 4;
+		end loop;
 		
-		wait until rising_edge(CLK_O) and dout_cnt = 7;
+		STB_O	<= '0';
+		wait until rising_edge(CLK_O) and dout_cnt = 31;
 		CYC_O	<= '0';
 
+		------------------------------------------------------------
 		wait for 3*CLK_PERIOD;
+		------------------------------------------------------------
+
 		wait until rising_edge(CLK_O);
 		-- 1-word burst cycle
 		CYC_O	<= '1';
@@ -355,10 +298,13 @@ STIMULUS: process
 		DAT_O	<= X"DEADBEEF";
 		wait until rising_edge(CLK_O) and SRDY_I = '1';
 		STB_O	<= '0';
-		wait until rising_edge(CLK_O) and ACK_I = '1';
+		wait until rising_edge(CLK_O);
 		CYC_O	<= '0';
 
+		------------------------------------------------------------
 		wait for 3*CLK_PERIOD;
+		------------------------------------------------------------
+
 		wait until rising_edge(CLK_O);
 		-- 1-word burst cycle
 		CYC_O	<= '1';
@@ -370,134 +316,536 @@ STIMULUS: process
 		wait until rising_edge(CLK_O) and ACK_I = '1';
 		CYC_O	<= '0';
 
-		-- 8-word burst cycle
+		------------------------------------------------------------
 		wait for 3*CLK_PERIOD;
+		------------------------------------------------------------
+
+		-- 8-word burst cycle
 		dout_rst	<= '1';
 		wait until rising_edge(CLK_O);
 		dout_rst	<= '0';
+
 		CYC_O	<= '1';
 		STB_O	<= '1';
 		WE_O	<= '0';
 		ADDR_O	<= X"0000_0000";
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		STB_O	<= '0';
-		MRDY_O	<= '0';
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		STB_O	<= '1';
-		MRDY_O	<= '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		STB_O	<= '0';
+
+		for i in 0 to 31 loop
+			wait until rising_edge(CLK_O) and SRDY_I = '1';
+			DAT_O	<= DAT_O + 1;
+			ADDR_O	<= ADDR_O + 4;
+		end loop;
 		
-		wait until rising_edge(CLK_O) and dout_cnt = 54;
+		STB_O	<= '0';
+		wait until rising_edge(CLK_O) and dout_cnt = 31;
 		CYC_O	<= '0';
 
+		------------------------------------------------------------
+		wait for 10*CLK_PERIOD;
+		------------------------------------------------------------
+
+		for k in 0 to 3 loop
+			------------------------------------------------------------
+--			wait for 3*CLK_PERIOD;
+			------------------------------------------------------------
+
+			-- 8-word burst cycle
+			dout_rst	<= '1';
+			wait until rising_edge(CLK_O);
+			dout_rst	<= '0';
+
+			CYC_O	<= '1';
+			STB_O	<= '1';
+			WE_O	<= '0';
+			ADDR_O	<= X"0000_0000";
+
+			for i in 0 to 7 loop
+				wait until rising_edge(CLK_O) and SRDY_I = '1';
+				DAT_O	<= DAT_O + 1;
+				ADDR_O	<= ADDR_O + 4;
+			end loop;
+
+			STB_O	<= '0';
+			wait until rising_edge(CLK_O) and dout_cnt = 7;
+			CYC_O	<= '0';
+
+			------------------------------------------------------------
+--			wait for 3*CLK_PERIOD;
+			------------------------------------------------------------
+
+			-- 8-word burst cycle
+			dout_rst	<= '1';
+			wait until rising_edge(CLK_O);
+			dout_rst	<= '0';
+
+			CYC_O	<= '1';
+			STB_O	<= '1';
+			WE_O	<= '0';
+			ADDR_O	<= X"0000_0400";
+
+			for i in 0 to 7 loop
+				wait until rising_edge(CLK_O) and SRDY_I = '1';
+				DAT_O	<= DAT_O + 1;
+				ADDR_O	<= ADDR_O + 4;
+			end loop;
+
+			STB_O	<= '0';
+			wait until rising_edge(CLK_O) and dout_cnt = 7;
+			CYC_O	<= '0';
+
+			------------------------------------------------------------
+--			wait for 3*CLK_PERIOD;
+			------------------------------------------------------------
+
+			-- 8-word burst cycle
+			dout_rst	<= '1';
+			wait until rising_edge(CLK_O);
+			dout_rst	<= '0';
+
+			CYC_O	<= '1';
+			STB_O	<= '1';
+			WE_O	<= '0';
+			ADDR_O	<= X"0000_0800";
+
+			for i in 0 to 7 loop
+				wait until rising_edge(CLK_O) and SRDY_I = '1';
+				DAT_O	<= DAT_O + 1;
+				ADDR_O	<= ADDR_O + 4;
+			end loop;
+
+			STB_O	<= '0';
+			wait until rising_edge(CLK_O) and dout_cnt = 7;
+			CYC_O	<= '0';
+
+			------------------------------------------------------------
+--			wait for 3*CLK_PERIOD;
+			------------------------------------------------------------
+
+			-- 8-word burst cycle
+			dout_rst	<= '1';
+			wait until rising_edge(CLK_O);
+			dout_rst	<= '0';
+
+			CYC_O	<= '1';
+			STB_O	<= '1';
+			WE_O	<= '0';
+			ADDR_O	<= X"0000_0C00";
+
+			for i in 0 to 7 loop
+				wait until rising_edge(CLK_O) and SRDY_I = '1';
+				DAT_O	<= DAT_O + 1;
+				ADDR_O	<= ADDR_O + 4;
+			end loop;
+
+			STB_O	<= '0';
+			wait until rising_edge(CLK_O) and dout_cnt = 7;
+			CYC_O	<= '0';
+		
+		end loop;
+
+		------------------------------------------------------------
+		wait for 10*CLK_PERIOD;
+		------------------------------------------------------------
+		
+		for k in 0 to 3 loop
+
+			-- 8-word burst cycle
+			dout_rst	<= '1';
+			wait until rising_edge(CLK_O);
+			dout_rst	<= '0';
+
+			CYC_O	<= '1';
+			STB_O	<= '1';
+			WE_O	<= '0';
+			ADDR_O	<= X"0000_1000";
+
+			for i in 0 to 7 loop
+				wait until rising_edge(CLK_O) and SRDY_I = '1';
+				DAT_O	<= DAT_O + 1;
+				ADDR_O	<= ADDR_O + 4;
+			end loop;
+
+			STB_O	<= '0';
+			wait until rising_edge(CLK_O) and dout_cnt = 7;
+			CYC_O	<= '0';
+
+			------------------------------------------------------------
+--			wait for 3*CLK_PERIOD;
+			------------------------------------------------------------
+
+			-- 8-word burst cycle
+			dout_rst	<= '1';
+			wait until rising_edge(CLK_O);
+			dout_rst	<= '0';
+
+			CYC_O	<= '1';
+			STB_O	<= '1';
+			WE_O	<= '0';
+			ADDR_O	<= X"0000_1400";
+
+			for i in 0 to 7 loop
+				wait until rising_edge(CLK_O) and SRDY_I = '1';
+				DAT_O	<= DAT_O + 1;
+				ADDR_O	<= ADDR_O + 4;
+			end loop;
+
+			STB_O	<= '0';
+			wait until rising_edge(CLK_O) and dout_cnt = 7;
+			CYC_O	<= '0';
+
+			------------------------------------------------------------
+--			wait for 3*CLK_PERIOD;
+			------------------------------------------------------------
+
+			-- 8-word burst cycle
+			dout_rst	<= '1';
+			wait until rising_edge(CLK_O);
+			dout_rst	<= '0';
+
+			CYC_O	<= '1';
+			STB_O	<= '1';
+			WE_O	<= '0';
+			ADDR_O	<= X"0000_1800";
+
+			for i in 0 to 7 loop
+				wait until rising_edge(CLK_O) and SRDY_I = '1';
+				DAT_O	<= DAT_O + 1;
+				ADDR_O	<= ADDR_O + 4;
+			end loop;
+
+			STB_O	<= '0';
+			wait until rising_edge(CLK_O) and dout_cnt = 7;
+			CYC_O	<= '0';
+
+			------------------------------------------------------------
+--			wait for 3*CLK_PERIOD;
+			------------------------------------------------------------
+
+			-- 8-word burst cycle
+			dout_rst	<= '1';
+			wait until rising_edge(CLK_O);
+			dout_rst	<= '0';
+
+			CYC_O	<= '1';
+			STB_O	<= '1';
+			WE_O	<= '0';
+			ADDR_O	<= X"0000_1C00";
+
+			for i in 0 to 7 loop
+				wait until rising_edge(CLK_O) and SRDY_I = '1';
+				DAT_O	<= DAT_O + 1;
+				ADDR_O	<= ADDR_O + 4;
+			end loop;
+
+			STB_O	<= '0';
+			wait until rising_edge(CLK_O) and dout_cnt = 7;
+			CYC_O	<= '0';
+		
+		end loop;
+
+		------------------------------------------------------------
+		wait for 10*CLK_PERIOD;
+		------------------------------------------------------------
+
+		for k in 0 to 3 loop
+			------------------------------------------------------------
+--			wait for 3*CLK_PERIOD;
+			------------------------------------------------------------
+
+			-- 8-word burst cycle
+			dout_rst	<= '1';
+			wait until rising_edge(CLK_O);
+			dout_rst	<= '0';
+
+			CYC_O	<= '1';
+			STB_O	<= '1';
+			WE_O	<= '1';
+			ADDR_O	<= X"0000_0000";
+
+			for i in 0 to 7 loop
+				wait until rising_edge(CLK_O) and SRDY_I = '1';
+				DAT_O	<= DAT_O + 1;
+				ADDR_O	<= ADDR_O + 4;
+			end loop;
+
+			STB_O	<= '0';
+			wait until rising_edge(CLK_O);
+			CYC_O	<= '0';
+
+			------------------------------------------------------------
+--			wait for 3*CLK_PERIOD;
+			------------------------------------------------------------
+
+			-- 8-word burst cycle
+			dout_rst	<= '1';
+			wait until rising_edge(CLK_O);
+			dout_rst	<= '0';
+
+			CYC_O	<= '1';
+			STB_O	<= '1';
+			WE_O	<= '1';
+			ADDR_O	<= X"0000_0400";
+
+			for i in 0 to 7 loop
+				wait until rising_edge(CLK_O) and SRDY_I = '1';
+				DAT_O	<= DAT_O + 1;
+				ADDR_O	<= ADDR_O + 4;
+			end loop;
+
+			STB_O	<= '0';
+			wait until rising_edge(CLK_O);
+			CYC_O	<= '0';
+
+			------------------------------------------------------------
+--			wait for 3*CLK_PERIOD;
+			------------------------------------------------------------
+
+			-- 8-word burst cycle
+			dout_rst	<= '1';
+			wait until rising_edge(CLK_O);
+			dout_rst	<= '0';
+
+			CYC_O	<= '1';
+			STB_O	<= '1';
+			WE_O	<= '1';
+			ADDR_O	<= X"0000_0800";
+
+			for i in 0 to 7 loop
+				wait until rising_edge(CLK_O) and SRDY_I = '1';
+				DAT_O	<= DAT_O + 1;
+				ADDR_O	<= ADDR_O + 4;
+			end loop;
+
+			STB_O	<= '0';
+			wait until rising_edge(CLK_O);
+			CYC_O	<= '0';
+
+			------------------------------------------------------------
+--			wait for 3*CLK_PERIOD;
+			------------------------------------------------------------
+
+			-- 8-word burst cycle
+			dout_rst	<= '1';
+			wait until rising_edge(CLK_O);
+			dout_rst	<= '0';
+
+			CYC_O	<= '1';
+			STB_O	<= '1';
+			WE_O	<= '1';
+			ADDR_O	<= X"0000_0C00";
+
+			for i in 0 to 7 loop
+				wait until rising_edge(CLK_O) and SRDY_I = '1';
+				DAT_O	<= DAT_O + 1;
+				ADDR_O	<= ADDR_O + 4;
+			end loop;
+
+			STB_O	<= '0';
+			wait until rising_edge(CLK_O);
+			CYC_O	<= '0';
+		
+		end loop;
+
+		------------------------------------------------------------
+		wait for 10*CLK_PERIOD;
+		------------------------------------------------------------
+		
+		for k in 0 to 3 loop
+
+			-- 8-word burst cycle
+			dout_rst	<= '1';
+			wait until rising_edge(CLK_O);
+			dout_rst	<= '0';
+
+			CYC_O	<= '1';
+			STB_O	<= '1';
+			WE_O	<= '1';
+			ADDR_O	<= X"0000_1000";
+
+			for i in 0 to 7 loop
+				wait until rising_edge(CLK_O) and SRDY_I = '1';
+				DAT_O	<= DAT_O + 1;
+				ADDR_O	<= ADDR_O + 4;
+			end loop;
+
+			STB_O	<= '0';
+			wait until rising_edge(CLK_O);
+			CYC_O	<= '0';
+
+			------------------------------------------------------------
+--			wait for 3*CLK_PERIOD;
+			------------------------------------------------------------
+
+			-- 8-word burst cycle
+			dout_rst	<= '1';
+			wait until rising_edge(CLK_O);
+			dout_rst	<= '0';
+
+			CYC_O	<= '1';
+			STB_O	<= '1';
+			WE_O	<= '1';
+			ADDR_O	<= X"0000_1400";
+
+			for i in 0 to 7 loop
+				wait until rising_edge(CLK_O) and SRDY_I = '1';
+				DAT_O	<= DAT_O + 1;
+				ADDR_O	<= ADDR_O + 4;
+			end loop;
+
+			STB_O	<= '0';
+			wait until rising_edge(CLK_O);
+			CYC_O	<= '0';
+
+			------------------------------------------------------------
+--			wait for 3*CLK_PERIOD;
+			------------------------------------------------------------
+
+			-- 8-word burst cycle
+			dout_rst	<= '1';
+			wait until rising_edge(CLK_O);
+			dout_rst	<= '0';
+
+			CYC_O	<= '1';
+			STB_O	<= '1';
+			WE_O	<= '1';
+			ADDR_O	<= X"0000_1800";
+
+			for i in 0 to 7 loop
+				wait until rising_edge(CLK_O) and SRDY_I = '1';
+				DAT_O	<= DAT_O + 1;
+				ADDR_O	<= ADDR_O + 4;
+			end loop;
+
+			STB_O	<= '0';
+			wait until rising_edge(CLK_O);
+			CYC_O	<= '0';
+
+			------------------------------------------------------------
+--			wait for 3*CLK_PERIOD;
+			------------------------------------------------------------
+
+			-- 8-word burst cycle
+			dout_rst	<= '1';
+			wait until rising_edge(CLK_O);
+			dout_rst	<= '0';
+
+			CYC_O	<= '1';
+			STB_O	<= '1';
+			WE_O	<= '1';
+			ADDR_O	<= X"0000_1C00";
+
+			for i in 0 to 7 loop
+				wait until rising_edge(CLK_O) and SRDY_I = '1';
+				DAT_O	<= DAT_O + 1;
+				ADDR_O	<= ADDR_O + 4;
+			end loop;
+
+			STB_O	<= '0';
+			wait until rising_edge(CLK_O);
+			CYC_O	<= '0';
+		
+		end loop;
+
+		------------------------------------------------------------
+		wait for 10*CLK_PERIOD;
+		------------------------------------------------------------
+		
+		for k in 0 to 3 loop
+
+			-- 8-word burst cycle
+			dout_rst	<= '1';
+			wait until rising_edge(CLK_O);
+			dout_rst	<= '0';
+
+			CYC_O	<= '1';
+			STB_O	<= '1';
+			WE_O	<= '0';
+			ADDR_O	<= X"0000_1000";
+
+			for i in 0 to 7 loop
+				wait until rising_edge(CLK_O) and SRDY_I = '1';
+				DAT_O	<= DAT_O + 1;
+				ADDR_O	<= ADDR_O + 4;
+			end loop;
+
+			STB_O	<= '0';
+			wait until rising_edge(CLK_O) and dout_cnt = 7;
+			CYC_O	<= '0';
+
+			------------------------------------------------------------
+--			wait for 3*CLK_PERIOD;
+			------------------------------------------------------------
+
+			-- 8-word burst cycle
+			dout_rst	<= '1';
+			wait until rising_edge(CLK_O);
+			dout_rst	<= '0';
+
+			CYC_O	<= '1';
+			STB_O	<= '1';
+			WE_O	<= '0';
+			ADDR_O	<= X"0000_1400";
+
+			for i in 0 to 7 loop
+				wait until rising_edge(CLK_O) and SRDY_I = '1';
+				DAT_O	<= DAT_O + 1;
+				ADDR_O	<= ADDR_O + 4;
+			end loop;
+
+			STB_O	<= '0';
+			wait until rising_edge(CLK_O) and dout_cnt = 7;
+			CYC_O	<= '0';
+
+			------------------------------------------------------------
+--			wait for 3*CLK_PERIOD;
+			------------------------------------------------------------
+
+			-- 8-word burst cycle
+			dout_rst	<= '1';
+			wait until rising_edge(CLK_O);
+			dout_rst	<= '0';
+
+			CYC_O	<= '1';
+			STB_O	<= '1';
+			WE_O	<= '0';
+			ADDR_O	<= X"0000_1800";
+
+			for i in 0 to 7 loop
+				wait until rising_edge(CLK_O) and SRDY_I = '1';
+				DAT_O	<= DAT_O + 1;
+				ADDR_O	<= ADDR_O + 4;
+			end loop;
+
+			STB_O	<= '0';
+			wait until rising_edge(CLK_O) and dout_cnt = 7;
+			CYC_O	<= '0';
+
+			------------------------------------------------------------
+--			wait for 3*CLK_PERIOD;
+			------------------------------------------------------------
+
+			-- 8-word burst cycle
+			dout_rst	<= '1';
+			wait until rising_edge(CLK_O);
+			dout_rst	<= '0';
+
+			CYC_O	<= '1';
+			STB_O	<= '1';
+			WE_O	<= '0';
+			ADDR_O	<= X"0000_1C00";
+
+			for i in 0 to 7 loop
+				wait until rising_edge(CLK_O) and SRDY_I = '1';
+				DAT_O	<= DAT_O + 1;
+				ADDR_O	<= ADDR_O + 4;
+			end loop;
+
+			STB_O	<= '0';
+			wait until rising_edge(CLK_O) and dout_cnt = 7;
+			CYC_O	<= '0';
+		
+		end loop;
+
 		wait; 
 	
 	end process;