jens/vhdl
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

- fixed synth project after fifo refactoring

Browse Source 
- used _ld roms

git-svn-id: http://moon:8086/svn/vhdl/trunk@1617 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2021-03-31 19:54:32 +00:00
parent 1864b98e55
commit 2721d59449
1 changed files with 4 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files
projects/vga_ctrl/syn/ise/project/vga_ctrl_sys.prj
+4 -2
View File
@@ -10,6 +10,8 @@ vhdl work "../../../../lib/rams/xilinx/src/dpram_1w1r2c_ra.vhd"
vhdl work "../../../../lib/FIFO/src/fifo_ctrl_pkg.vhd"
vhdl work "../../../../lib/FIFO/src/gray_counter.vhd"
vhdl work "../../../../lib/FIFO/src/fifo_async_ctrl.vhd"
vhdl work "../../../../lib/FIFO/src/fifo_async_stage.vhd"
vhdl work "../../../../lib/FIFO/src/reg_stage.vhd"
vhdl work "../../../../lib/FIFO/src/fifo_async.vhd"
vhdl work "../../../../lib/CPUs/JCpu/src/core/cpu_pkg.vhd"
vhdl work "../../../../lib/CPUs/JCpu/src/core/cpu.vhd"
@@ -22,8 +24,8 @@ vhdl work "../../../../lib/CPUs/JCpu/src/core/pc.vhd"
vhdl work "../../../../lib/CPUs/JCpu/src/core/reg_dual.vhd"
vhdl work "../../../../lib/CPUs/JCpu/src/core/stack_ctrl.vhd"
vhdl work "../../../../lib/clock/xilinx/src/clockgen.vhd"
vhdl work "../../src/main_xrom.vhdl"
vhdl work "../../src/main_irom.vhdl"
vhdl work "../../src/main_xrom_ld.vhdl"
vhdl work "../../src/main_irom_ld.vhdl"
vhdl work "../../src/cpu_embedded.vhd"
vhdl work "../../src/vga_ctrl_top.vhd"
vhdl work "../../src/vga_ctrl_sys.vhd"