jens 2721d59449 - fixed synth project after fifo refactoring ...

- used _ld roms

git-svn-id: http://moon:8086/svn/vhdl/trunk@1617 cc03376c-175c-47c8-b038-4cd826a8556b

2021-03-31 19:54:32 +00:00

Common

- removed old wave select

2021-03-28 17:38:25 +00:00

lib

- removed half-cycle register for pc.branch_take

2021-03-31 14:04:22 +00:00

make

- remove unrelated path

2021-03-30 15:42:52 +00:00

projects

- fixed synth project after fifo refactoring

2021-03-31 19:54:32 +00:00

Makefile

- refactored ISE makefiles

2021-03-29 12:49:42 +00:00

S

Description

No description provided

23 MiB

Languages

VHDL 90.2%

Verilog 4.2%

Tcl 2.5%

SystemVerilog 0.9%

IGOR Pro 0.5%

Other 1.3%