From 2721d59449b6f3c0300c07630369ebe16d3f95fb Mon Sep 17 00:00:00 2001
From: Jens Ahrensfeld <jens@jayfield.org>
Date: Wed, 31 Mar 2021 19:54:32 +0000
Subject: [PATCH] - fixed synth project after fifo refactoring - used _ld roms

git-svn-id: http://moon:8086/svn/vhdl/trunk@1617 cc03376c-175c-47c8-b038-4cd826a8556b
---
 projects/vga_ctrl/syn/ise/project/vga_ctrl_sys.prj | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/projects/vga_ctrl/syn/ise/project/vga_ctrl_sys.prj b/projects/vga_ctrl/syn/ise/project/vga_ctrl_sys.prj
index 8b337ee..df52c76 100644
--- a/projects/vga_ctrl/syn/ise/project/vga_ctrl_sys.prj
+++ b/projects/vga_ctrl/syn/ise/project/vga_ctrl_sys.prj
@@ -10,6 +10,8 @@ vhdl work "../../../../lib/rams/xilinx/src/dpram_1w1r2c_ra.vhd"
 vhdl work "../../../../lib/FIFO/src/fifo_ctrl_pkg.vhd"
 vhdl work "../../../../lib/FIFO/src/gray_counter.vhd"
 vhdl work "../../../../lib/FIFO/src/fifo_async_ctrl.vhd"
+vhdl work "../../../../lib/FIFO/src/fifo_async_stage.vhd"
+vhdl work "../../../../lib/FIFO/src/reg_stage.vhd"
 vhdl work "../../../../lib/FIFO/src/fifo_async.vhd"
 vhdl work "../../../../lib/CPUs/JCpu/src/core/cpu_pkg.vhd"
 vhdl work "../../../../lib/CPUs/JCpu/src/core/cpu.vhd"
@@ -22,8 +24,8 @@ vhdl work "../../../../lib/CPUs/JCpu/src/core/pc.vhd"
 vhdl work "../../../../lib/CPUs/JCpu/src/core/reg_dual.vhd"
 vhdl work "../../../../lib/CPUs/JCpu/src/core/stack_ctrl.vhd"
 vhdl work "../../../../lib/clock/xilinx/src/clockgen.vhd"
-vhdl work "../../src/main_xrom.vhdl"
-vhdl work "../../src/main_irom.vhdl"
+vhdl work "../../src/main_xrom_ld.vhdl"
+vhdl work "../../src/main_irom_ld.vhdl"
 vhdl work "../../src/cpu_embedded.vhd"
 vhdl work "../../src/vga_ctrl_top.vhd"
 vhdl work "../../src/vga_ctrl_sys.vhd"