[JUART]

- fixed RX incorrect behavior with BAUD_DIV > 1
- added baud rate generator to TB
- added TB with TX and RX

git-svn-id: http://moon:8086/svn/vhdl/trunk@1343 cc03376c-175c-47c8-b038-4cd826a8556b

lib/uart/tb_juart_tx.vhd

@@ -32,6 +32,7 @@ architecture behave of tb_juart_tx is
 
 	-- Number of user data words for simulation
 	constant CLK_PERIOD		: time := 10 ns;
+	constant BAUD_DIV		: natural := 2;
 
 	signal rst				: std_logic := '1';  
 	signal clk				: std_logic := '1';  
@@ -41,6 +42,8 @@ architecture behave of tb_juart_tx is
 	signal Tx_complete		: std_logic;  
 	signal data_in			: unsigned(7 downto 0) := (others => '0');
 
+	signal baud_count		: unsigned(15 downto 0);
+	signal baud_reg			: unsigned(15 downto 0) := to_unsigned(BAUD_DIV-1, baud_count'length);
 begin
 
 inst_juart_tx : entity work.juart_tx
@@ -62,6 +65,22 @@ CLK_GEN: process
 		clk <= not clk;
 	end process;
 
+baud_timer:
+process(clk)
+begin
+	if rising_edge(clk) then
+		en_16_x_baud <= '0';
+		if rst = '1' then
+			baud_count <= (others => '0');
+		elsif baud_count = baud_reg then
+			baud_count <= (others => '0');
+			en_16_x_baud <= '1';
+		else
+			baud_count <= baud_count + 1;
+		end if;
+	end if;
+end process;
+
 ------------------------------------------------------------------------------------------
 
 STIMULUS: process