diff --git a/lib/uart/juart_rx.vhd b/lib/uart/juart_rx.vhd index 177ac58..9295369 100644 --- a/lib/uart/juart_rx.vhd +++ b/lib/uart/juart_rx.vhd @@ -65,7 +65,7 @@ signal state_next : state_t; -- begin -bit_sample <= sample_count(OVERSAMPLING/2); +bit_sample <= sample_count(OVERSAMPLING/2) and en_16_x_baud; is_idle <= '1' when idle_count = 0 else '0'; data_out_reg: @@ -138,7 +138,7 @@ begin if rising_edge(clk) then if rst = '1' then shiftreg <= (others => '0'); - elsif shiftreg_en = '1' and bit_sample = '1' then + elsif shiftreg_en = '1' and bit_sample = '1' and en_16_x_baud = '1' then shiftreg <= shiftreg(shiftreg'left-1 downto 0) & serial_in; end if; end if; @@ -162,7 +162,7 @@ begin if rising_edge(clk) then if bit_count_rst = '1' then bit_count <= 0; - elsif bit_count /= bit_count_t'high and bit_sample = '1' then + elsif bit_count /= bit_count_t'high and bit_sample = '1' and en_16_x_baud = '1' then bit_count <= bit_count + 1; end if; end if; @@ -174,7 +174,7 @@ begin if rising_edge(clk) then if serial_in = '0' then idle_count <= idle_count_t'high; - elsif idle_count /= 0 then + elsif idle_count /= 0 and en_16_x_baud = '1' then idle_count <= idle_count - 1; end if; end if; diff --git a/lib/uart/sim/tb_juart_rx.fdo b/lib/uart/sim/tb_juart_rx.fdo index 10889a5..2e6e1b4 100644 --- a/lib/uart/sim/tb_juart_rx.fdo +++ b/lib/uart/sim/tb_juart_rx.fdo @@ -11,4 +11,4 @@ do {tb_juart_rx.wdo} view wave view structure view signals -run 6.0us +run 7.0us diff --git a/lib/uart/sim/tb_juart_rx.wdo b/lib/uart/sim/tb_juart_rx.wdo index 6b6c661..889e39b 100644 --- a/lib/uart/sim/tb_juart_rx.wdo +++ b/lib/uart/sim/tb_juart_rx.wdo @@ -20,7 +20,7 @@ add wave -noupdate -format Logic /tb_juart_rx/inst_juart_rx/sample_count_rst add wave -noupdate -format Logic /tb_juart_rx/inst_juart_rx/data_strobe add wave -noupdate -format Literal -radix hexadecimal /tb_juart_rx/data_out TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {362114 ps} 0} +WaveRestoreCursors {{Cursor 1} {5936632 ps} 0} configure wave -namecolwidth 150 configure wave -valuecolwidth 100 configure wave -justifyvalue left @@ -34,4 +34,4 @@ configure wave -gridperiod 1 configure wave -griddelta 40 configure wave -timeline 0 update -WaveRestoreZoom {0 ps} {6300 ns} +WaveRestoreZoom {0 ps} {7350 ns} diff --git a/lib/uart/sim/tb_juart_tx.fdo b/lib/uart/sim/tb_juart_tx.fdo index 9f76a06..1f0b372 100644 --- a/lib/uart/sim/tb_juart_tx.fdo +++ b/lib/uart/sim/tb_juart_tx.fdo @@ -11,4 +11,4 @@ do {tb_juart_tx.wdo} view wave view structure view signals -run 6.0us +run 10.0us diff --git a/lib/uart/sim/tb_juart_tx.wdo b/lib/uart/sim/tb_juart_tx.wdo index bc05d8f..d227228 100644 --- a/lib/uart/sim/tb_juart_tx.wdo +++ b/lib/uart/sim/tb_juart_tx.wdo @@ -16,7 +16,7 @@ add wave -noupdate -format Logic /tb_juart_tx/inst_juart_tx/shift_enable add wave -noupdate -format Literal -radix unsigned /tb_juart_tx/inst_juart_tx/shift_enable_count add wave -noupdate -format Literal -radix unsigned /tb_juart_tx/inst_juart_tx/bit_count TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {40000 ps} 0} +WaveRestoreCursors {{Cursor 1} {9812114 ps} 0} configure wave -namecolwidth 150 configure wave -valuecolwidth 100 configure wave -justifyvalue left @@ -30,4 +30,4 @@ configure wave -gridperiod 1 configure wave -griddelta 40 configure wave -timeline 0 update -WaveRestoreZoom {0 ps} {2100 ns} +WaveRestoreZoom {0 ps} {10500 ns} diff --git a/lib/uart/sim/tb_juart_tx_rx.fdo b/lib/uart/sim/tb_juart_tx_rx.fdo new file mode 100644 index 0000000..ccbe4bf --- /dev/null +++ b/lib/uart/sim/tb_juart_tx_rx.fdo @@ -0,0 +1,15 @@ +## NOTE: Do not edit this file. +## + +vlib work +vcom -explicit -93 "../juart_tx.vhd" +vcom -explicit -93 "../juart_rx.vhd" +vcom -explicit -93 "../tb_juart_tx_rx.vhd" + +#restart -force +vsim -t 1ps -lib work tb_juart_tx_rx +do {tb_juart_tx_rx.wdo} +view wave +view structure +view signals +run 10.0us diff --git a/lib/uart/sim/tb_juart_tx_rx.wdo b/lib/uart/sim/tb_juart_tx_rx.wdo new file mode 100644 index 0000000..1398efe --- /dev/null +++ b/lib/uart/sim/tb_juart_tx_rx.wdo @@ -0,0 +1,30 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate -format Logic /tb_juart_tx_rx/rst +add wave -noupdate -format Logic /tb_juart_tx_rx/clk +add wave -noupdate -format Logic /tb_juart_tx_rx/en_16_x_baud +add wave -noupdate -format Logic /tb_juart_tx_rx/send_character +add wave -noupdate -format Logic /tb_juart_tx_rx/serial_out +add wave -noupdate -format Logic /tb_juart_tx_rx/tx_complete +add wave -noupdate -format Literal -radix hexadecimal /tb_juart_tx_rx/data_in +add wave -noupdate -format Logic /tb_juart_tx_rx/serial_in +add wave -noupdate -format Logic /tb_juart_tx_rx/data_strobe +add wave -noupdate -format Literal -radix hexadecimal /tb_juart_tx_rx/data_out +add wave -noupdate -format Literal -radix hexadecimal /tb_juart_tx_rx/data_rx +add wave -noupdate -format Literal -radix hexadecimal /tb_juart_tx_rx/data_tx +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {8475278 ps} 0} +configure wave -namecolwidth 150 +configure wave -valuecolwidth 100 +configure wave -justifyvalue left +configure wave -signalnamewidth 1 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +update +WaveRestoreZoom {0 ps} {10500 ns} diff --git a/lib/uart/tb_juart_rx.vhd b/lib/uart/tb_juart_rx.vhd index b2811e0..5920829 100644 --- a/lib/uart/tb_juart_rx.vhd +++ b/lib/uart/tb_juart_rx.vhd @@ -32,6 +32,7 @@ architecture behave of tb_juart_rx is -- Number of user data words for simulation constant CLK_PERIOD : time := 10 ns; + constant BAUD_DIV : natural := 2; signal rst : std_logic := '1'; signal clk : std_logic := '1'; @@ -41,6 +42,8 @@ architecture behave of tb_juart_rx is signal data_out : unsigned(7 downto 0); signal serial_word : unsigned(7 downto 0) := X"AA"; + signal baud_count : unsigned(15 downto 0); + signal baud_reg : unsigned(15 downto 0) := to_unsigned(BAUD_DIV-1, baud_count'length); signal data_reg : unsigned(7 downto 0); begin @@ -68,6 +71,22 @@ PROC_DATAREG: process data_reg <= data_out; end process; +baud_timer: +process(clk) +begin + if rising_edge(clk) then + en_16_x_baud <= '0'; + if rst = '1' then + baud_count <= (others => '0'); + elsif baud_count = baud_reg then + baud_count <= (others => '0'); + en_16_x_baud <= '1'; + else + baud_count <= baud_count + 1; + end if; + end if; +end process; + ------------------------------------------------------------------------------------------ STIMULUS: process @@ -79,22 +98,22 @@ STIMULUS: process rst <= '0'; serial_word <= X"AA"; - wait for 16*CLK_PERIOD; + wait for 16*baud_div*CLK_PERIOD; serial_in <= '0'; - wait for 16*CLK_PERIOD; + wait for 16*baud_div*CLK_PERIOD; for i in serial_word'length-1 downto 0 loop serial_in <= serial_word(i); - wait for 16*CLK_PERIOD; + wait for 16*baud_div*CLK_PERIOD; end loop; serial_in <= '1'; - wait for 16*CLK_PERIOD; + wait for 16*baud_div*CLK_PERIOD; serial_word <= X"55"; serial_in <= '0'; - wait for 16*CLK_PERIOD; + wait for 16*baud_div*CLK_PERIOD; for i in serial_word'length-1 downto 0 loop serial_in <= serial_word(i); - wait for 16*CLK_PERIOD; + wait for 16*baud_div*CLK_PERIOD; end loop; serial_in <= '1'; wait; diff --git a/lib/uart/tb_juart_tx.vhd b/lib/uart/tb_juart_tx.vhd index cc11f9d..ca0f1f4 100644 --- a/lib/uart/tb_juart_tx.vhd +++ b/lib/uart/tb_juart_tx.vhd @@ -32,6 +32,7 @@ architecture behave of tb_juart_tx is -- Number of user data words for simulation constant CLK_PERIOD : time := 10 ns; + constant BAUD_DIV : natural := 2; signal rst : std_logic := '1'; signal clk : std_logic := '1'; @@ -41,6 +42,8 @@ architecture behave of tb_juart_tx is signal Tx_complete : std_logic; signal data_in : unsigned(7 downto 0) := (others => '0'); + signal baud_count : unsigned(15 downto 0); + signal baud_reg : unsigned(15 downto 0) := to_unsigned(BAUD_DIV-1, baud_count'length); begin inst_juart_tx : entity work.juart_tx @@ -62,6 +65,22 @@ CLK_GEN: process clk <= not clk; end process; +baud_timer: +process(clk) +begin + if rising_edge(clk) then + en_16_x_baud <= '0'; + if rst = '1' then + baud_count <= (others => '0'); + elsif baud_count = baud_reg then + baud_count <= (others => '0'); + en_16_x_baud <= '1'; + else + baud_count <= baud_count + 1; + end if; + end if; +end process; + ------------------------------------------------------------------------------------------ STIMULUS: process diff --git a/lib/uart/tb_juart_tx_rx.vhd b/lib/uart/tb_juart_tx_rx.vhd new file mode 100644 index 0000000..fd3df78 --- /dev/null +++ b/lib/uart/tb_juart_tx_rx.vhd @@ -0,0 +1,144 @@ +------------------------------------------------------------------------- +-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL +-- This file: cpu_embedded using cpu_core and rom +-- +-- Copyright (C) 2007 J. Ahrensfeld +-- +-- This program is free software: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see . +-- +-- For questions and ideas, please contact the author at jens@jayfield.org +-- +-------------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.numeric_std.ALL; + +entity tb_juart_tx_rx is +end; + +architecture behave of tb_juart_tx_rx is + + -- Number of user data words for simulation + constant CLK_PERIOD : time := 10 ns; + + -- Common + signal rst : std_logic := '1'; + signal clk : std_logic := '1'; + signal en_16_x_baud : std_logic := '1'; + + -- TX + signal send_character : std_logic := '0'; + signal serial_out : std_logic; + signal Tx_complete : std_logic; + signal data_in : unsigned(7 downto 0) := (others => '0'); + + -- RX + signal serial_in : std_logic := '1'; + signal data_strobe : std_logic; + signal data_out : unsigned(7 downto 0); + + -- Others + signal baud_count : unsigned(15 downto 0); + signal baudrate : unsigned(15 downto 0) := X"0001"; + signal data_rx : unsigned(7 downto 0); + signal data_tx : unsigned(7 downto 0) := X"AA"; + +begin + + serial_in <= serial_out; + +inst_juart_tx : entity work.juart_tx + PORT MAP + ( + rst => rst, + clk => clk, + en_16_x_baud => en_16_x_baud, + send_character => send_character, + Tx_complete => Tx_complete, + data_in => data_in, + serial_out => serial_out + ); + +inst_juart_rx : entity work.juart_rx + PORT MAP + ( + rst => rst, + clk => clk, + en_16_x_baud => en_16_x_baud, + data_strobe => data_strobe, + data_out => data_out, + serial_in => serial_in + ); + +CLK_GEN: process + begin + wait for CLK_PERIOD/2; + clk <= not clk; + end process; + +PROC_DATAREG: process + begin + wait until rising_edge(clk) and data_strobe = '1'; + data_rx <= data_out; + end process; + +baud_timer: +process(clk) +begin + if rising_edge(clk) then + en_16_x_baud <= '0'; + if rst = '1' then + baud_count <= (others => '0'); + elsif baud_count = baudrate then + baud_count <= (others => '0'); + en_16_x_baud <= '1'; + else + baud_count <= baud_count + 1; + end if; + end if; +end process; + +------------------------------------------------------------------------------------------ + +STIMULUS: process + + + begin + + wait for 3*CLK_PERIOD; + rst <= '0'; + wait for 3*CLK_PERIOD; + wait until rising_edge(clk); + data_in <= X"A5"; + wait until rising_edge(clk) and Tx_complete = '1'; + send_character <= '1'; + wait until rising_edge(clk) and Tx_complete = '0'; + send_character <= '0'; + wait until rising_edge(clk) and Tx_complete = '1'; + data_in <= X"AA"; + wait until rising_edge(clk) and Tx_complete = '1'; + send_character <= '1'; + wait until rising_edge(clk) and Tx_complete = '0'; + send_character <= '0'; + data_in <= X"55"; + wait until rising_edge(clk) and Tx_complete = '1'; + send_character <= '1'; + wait until rising_edge(clk) and Tx_complete = '0'; + send_character <= '0'; + wait; + + end process; + +end architecture behave;