jens 262d045890 [JUART]
- fixed RX incorrect behavior with BAUD_DIV > 1
- added baud rate generator to TB
- added TB with TX and RX

git-svn-id: http://moon:8086/svn/vhdl/trunk@1343 cc03376c-175c-47c8-b038-4cd826a8556b
2016-12-18 10:13:12 +00:00
2015-10-24 16:12:48 +00:00
2016-12-18 10:13:12 +00:00
2016-11-26 14:43:26 +00:00
S
Description
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23 MiB
Languages
VHDL 90.1%
Verilog 4.2%
Tcl 2.5%
SystemVerilog 0.8%
IGOR Pro 0.5%
Other 1.5%