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[JUART]

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- fixed RX incorrect behavior with BAUD_DIV > 1
- added baud rate generator to TB
- added TB with TX and RX

git-svn-id: http://moon:8086/svn/vhdl/trunk@1343 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2016-12-18 10:13:12 +00:00
parent f7af661eda
commit 262d045890
10 changed files with 243 additions and 16 deletions
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lib/uart/juart_rx.vhd
+4 -4
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@@ -65,7 +65,7 @@ signal state_next : state_t;
--
begin
bit_sample <= sample_count(OVERSAMPLING/2);
bit_sample <= sample_count(OVERSAMPLING/2) and en_16_x_baud;
is_idle <= '1' when idle_count = 0 else '0';
data_out_reg:
@@ -138,7 +138,7 @@ begin
if rising_edge(clk) then
if rst = '1' then
shiftreg <= (others => '0');
elsif shiftreg_en = '1' and bit_sample = '1' then
elsif shiftreg_en = '1' and bit_sample = '1' and en_16_x_baud = '1' then
shiftreg <= shiftreg(shiftreg'left-1 downto 0) & serial_in;
end if;
end if;
@@ -162,7 +162,7 @@ begin
if rising_edge(clk) then
if bit_count_rst = '1' then
bit_count <= 0;
elsif bit_count /= bit_count_t'high and bit_sample = '1' then
elsif bit_count /= bit_count_t'high and bit_sample = '1' and en_16_x_baud = '1' then
bit_count <= bit_count + 1;
end if;
end if;
@@ -174,7 +174,7 @@ begin
if rising_edge(clk) then
if serial_in = '0' then
idle_count <= idle_count_t'high;
elsif idle_count /= 0 then
elsif idle_count /= 0 and en_16_x_baud = '1' then
idle_count <= idle_count - 1;
end if;
end if;