jens/vhdl
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

VGA: refactored clocks and resets

Browse Source 
git-svn-id: http://moon:8086/svn/vhdl/trunk@1594 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2021-03-30 07:11:37 +00:00
parent 756dc0ec5a
commit 24e5cb75cb
3 changed files with 21 additions and 27 deletions
Download Patch File Download Diff File Expand all files Collapse all files
projects/vga_ctrl/src/tb_vga_ctrl.vhd
+9 -9
View File
@@ -49,8 +49,8 @@ ARCHITECTURE behavior OF tb_vga_ctrl IS
clk_in : IN std_logic; clk_in : IN std_logic;
-- VGA signals -- VGA signals
vga_clk_in : IN std_logic; vga_clk : IN std_logic;
vga_clk_ce : IN std_logic; vga_rst : IN std_logic;
vga_red : OUT unsigned(7 downto 0); vga_red : OUT unsigned(7 downto 0);
vga_green : OUT unsigned(7 downto 0); vga_green : OUT unsigned(7 downto 0);
vga_blue : OUT unsigned(7 downto 0); vga_blue : OUT unsigned(7 downto 0);
@@ -80,8 +80,8 @@ ARCHITECTURE behavior OF tb_vga_ctrl IS
SIGNAL btn : unsigned(4 downto 0) := (others => '0'); SIGNAL btn : unsigned(4 downto 0) := (others => '0');
--Outputs --Outputs
SIGNAL vga_clk_ce : std_logic := '1'; SIGNAL vga_rst : std_logic := '0';
SIGNAL vga_clk_in : std_logic := '0'; SIGNAL vga_clk : std_logic := '0';
SIGNAL vga_red : unsigned(7 downto 0); SIGNAL vga_red : unsigned(7 downto 0);
SIGNAL vga_green : unsigned(7 downto 0); SIGNAL vga_green : unsigned(7 downto 0);
SIGNAL vga_blue : unsigned(7 downto 0); SIGNAL vga_blue : unsigned(7 downto 0);
@@ -108,8 +108,8 @@ BEGIN
rst_in => rst_in, rst_in => rst_in,
clk_in => clk_in, clk_in => clk_in,
vga_clk_in => vga_clk_in, vga_clk => vga_clk,
vga_clk_ce => vga_clk_ce, vga_rst => vga_rst,
vga_red => vga_red, vga_red => vga_red,
vga_green => vga_green, vga_green => vga_green,
vga_blue => vga_blue, vga_blue => vga_blue,
@@ -123,15 +123,15 @@ BEGIN
led => led led => led
); );
clk : PROCESS proc_clk : PROCESS
BEGIN BEGIN
clk_in <= not clk_in; clk_in <= not clk_in;
wait for CLK_PERIOD/2; wait for CLK_PERIOD/2;
END PROCESS; END PROCESS;
vga_clk : PROCESS proc_vga_clk : PROCESS
BEGIN BEGIN
vga_clk_in <= not vga_clk_in; vga_clk <= not vga_clk;
wait for VGA_CLK_PERIOD/2; wait for VGA_CLK_PERIOD/2;
END PROCESS; END PROCESS;
projects/vga_ctrl/src/vga_ctrl_sys.vhd
+4 -6
View File
@@ -47,8 +47,8 @@ ARCHITECTURE behavior OF vga_ctrl_sys IS
clk_in : IN std_logic; clk_in : IN std_logic;
-- VGA signals -- VGA signals
vga_clk_in : IN std_logic; vga_clk : IN std_logic;
vga_clk_ce : IN std_logic; vga_rst : IN std_logic;
vga_red : OUT unsigned(7 downto 0); vga_red : OUT unsigned(7 downto 0);
vga_green : OUT unsigned(7 downto 0); vga_green : OUT unsigned(7 downto 0);
vga_blue : OUT unsigned(7 downto 0); vga_blue : OUT unsigned(7 downto 0);
@@ -68,7 +68,6 @@ ARCHITECTURE behavior OF vga_ctrl_sys IS
SIGNAL sys_rst : std_logic; SIGNAL sys_rst : std_logic;
SIGNAL vga_clk : std_logic; SIGNAL vga_clk : std_logic;
SIGNAL vga_rst : std_logic; SIGNAL vga_rst : std_logic;
SIGNAL vga_ce : std_logic;
constant vga_freq_MHz : real := real(tsvga.f_pxl_clk)/1.0E6; constant vga_freq_MHz : real := real(tsvga.f_pxl_clk)/1.0E6;
attribute KEEP : string; attribute KEEP : string;
@@ -78,7 +77,6 @@ ARCHITECTURE behavior OF vga_ctrl_sys IS
BEGIN BEGIN
sys_rst <= not sys_rst_n_in; sys_rst <= not sys_rst_n_in;
vga_ce <= not vga_rst;
sys_vga_clk <= vga_clk; sys_vga_clk <= vga_clk;
inst_vga_ctrl_top: vga_ctrl_top inst_vga_ctrl_top: vga_ctrl_top
@@ -91,8 +89,8 @@ BEGIN
rst_in => sys_rst, rst_in => sys_rst,
clk_in => sys_clk_in, clk_in => sys_clk_in,
vga_clk_in => vga_clk, vga_clk => vga_clk,
vga_clk_ce => vga_ce, vga_rst => vga_rst,
vga_red => sys_vga_red, vga_red => sys_vga_red,
vga_green => sys_vga_green, vga_green => sys_vga_green,
vga_blue => sys_vga_blue, vga_blue => sys_vga_blue,
projects/vga_ctrl/src/vga_ctrl_top.vhd
+8 -12
View File
@@ -35,8 +35,8 @@ entity vga_ctrl_top is
clk_in : in std_logic; clk_in : in std_logic;
-- VGA signals -- VGA signals
vga_clk_in : in std_logic; vga_clk : in std_logic;
vga_clk_ce : in std_logic; vga_rst : in std_logic;
vga_red : out unsigned(7 downto 0); vga_red : out unsigned(7 downto 0);
vga_green : out unsigned(7 downto 0); vga_green : out unsigned(7 downto 0);
vga_blue : out unsigned(7 downto 0); vga_blue : out unsigned(7 downto 0);
@@ -57,7 +57,6 @@ architecture Behavioral of vga_ctrl_top is
-- System signal -- System signal
signal rst : std_logic; signal rst : std_logic;
signal clk : std_logic; signal clk : std_logic;
signal vga_clk : std_logic;
-- Timing -- Timing
signal src_pos_x : natural range 0 to tsvga.ts_h.ncyc_scan-1; signal src_pos_x : natural range 0 to tsvga.ts_h.ncyc_scan-1;
@@ -70,7 +69,6 @@ architecture Behavioral of vga_ctrl_top is
signal color_op : color_op_t; signal color_op : color_op_t;
signal color_en : unsigned (VGA_NUM_CH-1 downto 0); signal color_en : unsigned (VGA_NUM_CH-1 downto 0);
signal stat_vga_rdy : std_logic;
signal stat_hready : std_logic; signal stat_hready : std_logic;
signal stat_vready : std_logic; signal stat_vready : std_logic;
signal stat_scan : std_logic; signal stat_scan : std_logic;
@@ -138,7 +136,6 @@ inst_vga_backend : entity work.vga_backend
ctrl_scan_en => ctrl_scan_en, ctrl_scan_en => ctrl_scan_en,
-- Status signals -- Status signals
stat_vga_rdy => stat_vga_rdy,
stat_scan => stat_scan, stat_scan => stat_scan,
stat_hsync => stat_hsync, stat_hsync => stat_hsync,
stat_vsync => stat_vsync, stat_vsync => stat_vsync,
@@ -150,8 +147,8 @@ inst_vga_backend : entity work.vga_backend
stat_vpos => stat_vpos, stat_vpos => stat_vpos,
-- VGA domain signals -- VGA domain signals
vga_clk_in => vga_clk_in, vga_clk => vga_clk,
vga_clk_ce => vga_clk_ce, vga_rst => vga_rst,
vga_red => vga_red, vga_red => vga_red,
vga_green => vga_green, vga_green => vga_green,
vga_blue => vga_blue, vga_blue => vga_blue,
@@ -161,7 +158,6 @@ inst_vga_backend : entity work.vga_backend
vga_vsync => vga_vsync vga_vsync => vga_vsync
); );
vga_clk <= vga_clk_in;
ctrl_scan_en <= '1'; ctrl_scan_en <= '1';
color_en(0) <= '1'; color_en(0) <= '1';
color_en(1) <= cg_draw; color_en(1) <= cg_draw;
@@ -232,7 +228,7 @@ inst_vga_backend : entity work.vga_backend
); );
--------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------
rst <= rst_in and stat_vga_rdy; rst <= rst_in;
clk <= clk_in; clk <= clk_in;
scan_rdy <= stat_hready and stat_vready; scan_rdy <= stat_hready and stat_vready;
@@ -264,7 +260,7 @@ cpu_reg_read:
when X"05" => -- 05 when X"05" => -- 05
reg := unsigned(dip); reg := unsigned(dip);
when X"0B" => when X"0B" =>
reg := "000000" & cg_rdy & stat_vga_rdy; reg := "000000" & cg_rdy & not vga_rst;
when others => null; when others => null;
end case; end case;
end if; end if;
@@ -337,10 +333,10 @@ cpu_reg_write:
cpu_start: process (clk) cpu_start: process (clk)
begin begin
if rising_edge(vga_clk) then if rising_edge(vga_clk) then
if rst = '1' then if vga_rst = '1' then
cpu_rst <= '1'; cpu_rst <= '1';
else else
cpu_rst <= not stat_vga_rdy; cpu_rst <= '0';
end if; end if;
end if; end if;
end process; end process;