From 24e5cb75cb0a64e35f4077e3ee9becf12433751c Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Tue, 30 Mar 2021 07:11:37 +0000 Subject: [PATCH] VGA: refactored clocks and resets git-svn-id: http://moon:8086/svn/vhdl/trunk@1594 cc03376c-175c-47c8-b038-4cd826a8556b --- projects/vga_ctrl/src/tb_vga_ctrl.vhd | 18 +++++++++--------- projects/vga_ctrl/src/vga_ctrl_sys.vhd | 10 ++++------ projects/vga_ctrl/src/vga_ctrl_top.vhd | 20 ++++++++------------ 3 files changed, 21 insertions(+), 27 deletions(-) diff --git a/projects/vga_ctrl/src/tb_vga_ctrl.vhd b/projects/vga_ctrl/src/tb_vga_ctrl.vhd index 704980a..0cf8c31 100644 --- a/projects/vga_ctrl/src/tb_vga_ctrl.vhd +++ b/projects/vga_ctrl/src/tb_vga_ctrl.vhd @@ -49,8 +49,8 @@ ARCHITECTURE behavior OF tb_vga_ctrl IS clk_in : IN std_logic; -- VGA signals - vga_clk_in : IN std_logic; - vga_clk_ce : IN std_logic; + vga_clk : IN std_logic; + vga_rst : IN std_logic; vga_red : OUT unsigned(7 downto 0); vga_green : OUT unsigned(7 downto 0); vga_blue : OUT unsigned(7 downto 0); @@ -80,8 +80,8 @@ ARCHITECTURE behavior OF tb_vga_ctrl IS SIGNAL btn : unsigned(4 downto 0) := (others => '0'); --Outputs - SIGNAL vga_clk_ce : std_logic := '1'; - SIGNAL vga_clk_in : std_logic := '0'; + SIGNAL vga_rst : std_logic := '0'; + SIGNAL vga_clk : std_logic := '0'; SIGNAL vga_red : unsigned(7 downto 0); SIGNAL vga_green : unsigned(7 downto 0); SIGNAL vga_blue : unsigned(7 downto 0); @@ -108,8 +108,8 @@ BEGIN rst_in => rst_in, clk_in => clk_in, - vga_clk_in => vga_clk_in, - vga_clk_ce => vga_clk_ce, + vga_clk => vga_clk, + vga_rst => vga_rst, vga_red => vga_red, vga_green => vga_green, vga_blue => vga_blue, @@ -123,15 +123,15 @@ BEGIN led => led ); - clk : PROCESS + proc_clk : PROCESS BEGIN clk_in <= not clk_in; wait for CLK_PERIOD/2; END PROCESS; - vga_clk : PROCESS + proc_vga_clk : PROCESS BEGIN - vga_clk_in <= not vga_clk_in; + vga_clk <= not vga_clk; wait for VGA_CLK_PERIOD/2; END PROCESS; diff --git a/projects/vga_ctrl/src/vga_ctrl_sys.vhd b/projects/vga_ctrl/src/vga_ctrl_sys.vhd index 8f97167..7ee8c75 100644 --- a/projects/vga_ctrl/src/vga_ctrl_sys.vhd +++ b/projects/vga_ctrl/src/vga_ctrl_sys.vhd @@ -47,8 +47,8 @@ ARCHITECTURE behavior OF vga_ctrl_sys IS clk_in : IN std_logic; -- VGA signals - vga_clk_in : IN std_logic; - vga_clk_ce : IN std_logic; + vga_clk : IN std_logic; + vga_rst : IN std_logic; vga_red : OUT unsigned(7 downto 0); vga_green : OUT unsigned(7 downto 0); vga_blue : OUT unsigned(7 downto 0); @@ -68,7 +68,6 @@ ARCHITECTURE behavior OF vga_ctrl_sys IS SIGNAL sys_rst : std_logic; SIGNAL vga_clk : std_logic; SIGNAL vga_rst : std_logic; - SIGNAL vga_ce : std_logic; constant vga_freq_MHz : real := real(tsvga.f_pxl_clk)/1.0E6; attribute KEEP : string; @@ -78,7 +77,6 @@ ARCHITECTURE behavior OF vga_ctrl_sys IS BEGIN sys_rst <= not sys_rst_n_in; - vga_ce <= not vga_rst; sys_vga_clk <= vga_clk; inst_vga_ctrl_top: vga_ctrl_top @@ -91,8 +89,8 @@ BEGIN rst_in => sys_rst, clk_in => sys_clk_in, - vga_clk_in => vga_clk, - vga_clk_ce => vga_ce, + vga_clk => vga_clk, + vga_rst => vga_rst, vga_red => sys_vga_red, vga_green => sys_vga_green, vga_blue => sys_vga_blue, diff --git a/projects/vga_ctrl/src/vga_ctrl_top.vhd b/projects/vga_ctrl/src/vga_ctrl_top.vhd index 8292cbc..27014be 100644 --- a/projects/vga_ctrl/src/vga_ctrl_top.vhd +++ b/projects/vga_ctrl/src/vga_ctrl_top.vhd @@ -35,8 +35,8 @@ entity vga_ctrl_top is clk_in : in std_logic; -- VGA signals - vga_clk_in : in std_logic; - vga_clk_ce : in std_logic; + vga_clk : in std_logic; + vga_rst : in std_logic; vga_red : out unsigned(7 downto 0); vga_green : out unsigned(7 downto 0); vga_blue : out unsigned(7 downto 0); @@ -57,7 +57,6 @@ architecture Behavioral of vga_ctrl_top is -- System signal signal rst : std_logic; signal clk : std_logic; - signal vga_clk : std_logic; -- Timing signal src_pos_x : natural range 0 to tsvga.ts_h.ncyc_scan-1; @@ -70,7 +69,6 @@ architecture Behavioral of vga_ctrl_top is signal color_op : color_op_t; signal color_en : unsigned (VGA_NUM_CH-1 downto 0); - signal stat_vga_rdy : std_logic; signal stat_hready : std_logic; signal stat_vready : std_logic; signal stat_scan : std_logic; @@ -138,7 +136,6 @@ inst_vga_backend : entity work.vga_backend ctrl_scan_en => ctrl_scan_en, -- Status signals - stat_vga_rdy => stat_vga_rdy, stat_scan => stat_scan, stat_hsync => stat_hsync, stat_vsync => stat_vsync, @@ -150,8 +147,8 @@ inst_vga_backend : entity work.vga_backend stat_vpos => stat_vpos, -- VGA domain signals - vga_clk_in => vga_clk_in, - vga_clk_ce => vga_clk_ce, + vga_clk => vga_clk, + vga_rst => vga_rst, vga_red => vga_red, vga_green => vga_green, vga_blue => vga_blue, @@ -161,7 +158,6 @@ inst_vga_backend : entity work.vga_backend vga_vsync => vga_vsync ); - vga_clk <= vga_clk_in; ctrl_scan_en <= '1'; color_en(0) <= '1'; color_en(1) <= cg_draw; @@ -232,7 +228,7 @@ inst_vga_backend : entity work.vga_backend ); --------------------------------------------------------------------------------------------- - rst <= rst_in and stat_vga_rdy; + rst <= rst_in; clk <= clk_in; scan_rdy <= stat_hready and stat_vready; @@ -264,7 +260,7 @@ cpu_reg_read: when X"05" => -- 05 reg := unsigned(dip); when X"0B" => - reg := "000000" & cg_rdy & stat_vga_rdy; + reg := "000000" & cg_rdy & not vga_rst; when others => null; end case; end if; @@ -337,10 +333,10 @@ cpu_reg_write: cpu_start: process (clk) begin if rising_edge(vga_clk) then - if rst = '1' then + if vga_rst = '1' then cpu_rst <= '1'; else - cpu_rst <= not stat_vga_rdy; + cpu_rst <= '0'; end if; end if; end process;