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VGA: refactored clocks and resets

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git-svn-id: http://moon:8086/svn/vhdl/trunk@1594 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2021-03-30 07:11:37 +00:00
parent 756dc0ec5a
commit 24e5cb75cb
3 changed files with 21 additions and 27 deletions
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projects/vga_ctrl/src/vga_ctrl_top.vhd
+8 -12
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@@ -35,8 +35,8 @@ entity vga_ctrl_top is
clk_in : in std_logic;
-- VGA signals
vga_clk_in : in std_logic;
vga_clk_ce : in std_logic;
vga_clk : in std_logic;
vga_rst : in std_logic;
vga_red : out unsigned(7 downto 0);
vga_green : out unsigned(7 downto 0);
vga_blue : out unsigned(7 downto 0);
@@ -57,7 +57,6 @@ architecture Behavioral of vga_ctrl_top is
-- System signal
signal rst : std_logic;
signal clk : std_logic;
signal vga_clk : std_logic;
-- Timing
signal src_pos_x : natural range 0 to tsvga.ts_h.ncyc_scan-1;
@@ -70,7 +69,6 @@ architecture Behavioral of vga_ctrl_top is
signal color_op : color_op_t;
signal color_en : unsigned (VGA_NUM_CH-1 downto 0);
signal stat_vga_rdy : std_logic;
signal stat_hready : std_logic;
signal stat_vready : std_logic;
signal stat_scan : std_logic;
@@ -138,7 +136,6 @@ inst_vga_backend : entity work.vga_backend
ctrl_scan_en => ctrl_scan_en,
-- Status signals
stat_vga_rdy => stat_vga_rdy,
stat_scan => stat_scan,
stat_hsync => stat_hsync,
stat_vsync => stat_vsync,
@@ -150,8 +147,8 @@ inst_vga_backend : entity work.vga_backend
stat_vpos => stat_vpos,
-- VGA domain signals
vga_clk_in => vga_clk_in,
vga_clk_ce => vga_clk_ce,
vga_clk => vga_clk,
vga_rst => vga_rst,
vga_red => vga_red,
vga_green => vga_green,
vga_blue => vga_blue,
@@ -161,7 +158,6 @@ inst_vga_backend : entity work.vga_backend
vga_vsync => vga_vsync
);
vga_clk <= vga_clk_in;
ctrl_scan_en <= '1';
color_en(0) <= '1';
color_en(1) <= cg_draw;
@@ -232,7 +228,7 @@ inst_vga_backend : entity work.vga_backend
);
---------------------------------------------------------------------------------------------
rst <= rst_in and stat_vga_rdy;
rst <= rst_in;
clk <= clk_in;
scan_rdy <= stat_hready and stat_vready;
@@ -264,7 +260,7 @@ cpu_reg_read:
when X"05" => -- 05
reg := unsigned(dip);
when X"0B" =>
reg := "000000" & cg_rdy & stat_vga_rdy;
reg := "000000" & cg_rdy & not vga_rst;
when others => null;
end case;
end if;
@@ -337,10 +333,10 @@ cpu_reg_write:
cpu_start: process (clk)
begin
if rising_edge(vga_clk) then
if rst = '1' then
if vga_rst = '1' then
cpu_rst <= '1';
else
cpu_rst <= not stat_vga_rdy;
cpu_rst <= '0';
end if;
end if;
end process;