From 1f387fdd7528ff825de081994a7871b31510f267 Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Tue, 24 Nov 2009 11:35:08 +0000 Subject: [PATCH] - Loads image for bugfix: instructions uncached LW => cached LW (with cache-miss) was buggy. Committed on the Free edition of March Hare Software CVSNT Server. Upgrade to CVS Suite for more features and support: http://march-hare.com/cvsnt/ git-svn-id: http://moon:8086/svn/vhdl/trunk@682 cc03376c-175c-47c8-b038-4cd826a8556b --- lib/CPUs/MIPS/src/tb_mips_top.vhd | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/lib/CPUs/MIPS/src/tb_mips_top.vhd b/lib/CPUs/MIPS/src/tb_mips_top.vhd index 87ea97e..9c80e43 100644 --- a/lib/CPUs/MIPS/src/tb_mips_top.vhd +++ b/lib/CPUs/MIPS/src/tb_mips_top.vhd @@ -394,7 +394,7 @@ SRAM_WRITE: FLASH_READ: process(rst, flash_cs_n, flash_oe_n, flash_a) type file_t is file of integer; - file load_flash : file_t open read_mode is "lwl.flash.bin"; + file load_flash : file_t open read_mode is "ucb.elf.flash.bin"; variable instr : integer; variable index : natural; variable temp : signed(31 downto 0); @@ -441,7 +441,7 @@ STIMULUS: process rst <= '0'; wait for 778254*CLK_PERIOD; wait until rising_edge(clk); - nmi <= '1'; + nmi <= '0'; wait for 3000*CLK_PERIOD; wait until rising_edge(clk); nmi <= '0';