From 191646cc73424ed012b357b7cb4c007c6f3637ea Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Sun, 28 Jul 2013 17:00:21 +0000 Subject: [PATCH] - reg_uart_tx is also written in simulation mode. Good for debugging. Committed on the Free edition of March Hare Software CVSNT Server. Upgrade to CVS Suite for more features and support: http://march-hare.com/cvsnt/ git-svn-id: http://moon:8086/svn/vhdl/trunk@987 cc03376c-175c-47c8-b038-4cd826a8556b --- lib/uart/uart_wb.vhd | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/uart/uart_wb.vhd b/lib/uart/uart_wb.vhd index 55cad91..6cb13d5 100644 --- a/lib/uart/uart_wb.vhd +++ b/lib/uart/uart_wb.vhd @@ -102,6 +102,7 @@ registers_write: case ADDR_I(5 downto 2) is when "0000" => + reg_uart_tx <= DAT_I(7 downto 0); if simulate_tx then if DAT_I(7 downto 0) /= X"0D" then write(L, character'val(to_integer(DAT_I(7 downto 0)))); @@ -111,7 +112,6 @@ registers_write: end if; else reg_we_uart_tx <= '1'; - reg_uart_tx <= DAT_I(7 downto 0); end if; when "0001" =>