From 0ea7ced5e319c6090f144d8e419d575a4e653c7e Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Sun, 19 Oct 2008 21:11:46 +0000 Subject: [PATCH] - Removed linefifo and clockgen (=> frontend and top) git-svn-id: http://moon:8086/svn/vhdl/trunk@80 cc03376c-175c-47c8-b038-4cd826a8556b --- lib/VGA_ctrl/src/vga_backend.vhd | 83 +++++++++++--------------------- 1 file changed, 29 insertions(+), 54 deletions(-) diff --git a/lib/VGA_ctrl/src/vga_backend.vhd b/lib/VGA_ctrl/src/vga_backend.vhd index 2994eec..8cf10a1 100644 --- a/lib/VGA_ctrl/src/vga_backend.vhd +++ b/lib/VGA_ctrl/src/vga_backend.vhd @@ -27,9 +27,6 @@ entity vga_backend is Generic ( sys_freq : integer := 100E6; - fifo_depth : integer := 2048; - fifo_almost_full_thresh : natural := 2000; - fifo_almost_empty_thresh : natural := 48; tsvga : vga_timespec_t := ts_vga_800_600_72 ); Port @@ -37,19 +34,18 @@ entity vga_backend is -- System signals sys_rst : in std_logic; sys_clk : in std_logic; - vga_ready : out std_logic; - -- Buffered channel (Graphics plane) - color_in : in color_t; - color_fifo_we : in std_logic; - color_fifo_full : out std_logic; - color_fifo_afull : out std_logic; + -- Color channels + color_in : in color_array_t; + color_op : in color_op_t; + color_en : unsigned (VGA_NUM_CH-1 downto 0); + + -- Control signals + ctrl_scan_en : in std_logic; - -- Direct channel (Character plane) - direct_color_in : in color_t; - direct_draw_en : in std_logic; - -- Status signals + stat_vga_rdy : out std_logic; + stat_scan : out std_logic; stat_hsync : out std_logic; stat_vsync : out std_logic; stat_hready : out std_logic; @@ -61,7 +57,9 @@ entity vga_backend is -- VGA domain signals vga_clk_out : out std_logic; - vga_color_out : out color_t; + vga_red : out unsigned(7 downto 0); + vga_green : out unsigned(7 downto 0); + vga_blue : out unsigned(7 downto 0); vga_blank_n : out std_logic; vga_sync_n : out std_logic; vga_hsync : out std_logic; @@ -72,10 +70,6 @@ end vga_backend; architecture Behavioral of vga_backend is signal scan_enable : std_logic; - signal fifo_full : std_logic; - signal fifo_empty : std_logic; - signal fifo_almost_empty : std_logic; - signal fifo_almost_full : std_logic; signal is_scan : std_logic; signal is_hscan : std_logic; signal is_vscan : std_logic; @@ -83,7 +77,6 @@ architecture Behavioral of vga_backend is signal vsync : std_logic; signal hready : std_logic; signal vready : std_logic; - signal color : color_t; signal vga_clk : std_logic; signal dcm_locked : std_logic; signal rst : std_logic; @@ -91,9 +84,8 @@ architecture Behavioral of vga_backend is begin vga_clk_out <= vga_clk; - vga_ready <= dcm_locked; - inst_clkgen: entity work.clkgen +inst_clkgen: entity work.clkgen GENERIC MAP ( sys_freq => sys_freq, @@ -107,7 +99,7 @@ begin dcm_locked => dcm_locked ); - inst_vga_timing: entity work.vga_timing +inst_vga_timing: entity work.vga_timing GENERIC MAP ( tsvga => tsvga @@ -127,44 +119,21 @@ begin scan_rdy_v => vready ); - inst_linefifo: entity work.linefifo - GENERIC MAP - ( - depth => fifo_depth, - almost_full_thresh => fifo_almost_full_thresh, - almost_empty_thresh => fifo_almost_empty_thresh - ) - PORT MAP( - rst => sys_rst, - clk_w => sys_clk, - clk_r => vga_clk, - we_w => color_fifo_we, - re_r => is_scan, - color_w => color_in, - color_r => color, - fifo_full => fifo_full, - fifo_empty => fifo_empty, - fifo_afull => fifo_almost_full, - fifo_aempty => fifo_almost_empty - - ); - --------------------------------------------------------------------------------------------- rst <= not dcm_locked; + stat_vga_rdy <= dcm_locked; stat_hsync <= hsync; stat_vsync <= vsync; stat_hscan <= is_hscan; stat_vscan <= is_vscan; stat_hready <= hready; stat_vready <= vready; + stat_scan <= is_scan; vga_blank_n <= '1'; vga_sync_n <= '0'; is_scan <= is_hscan and is_vscan and scan_enable; - color_fifo_full <= fifo_full; - color_fifo_afull <= fifo_almost_full; - --------------------------------------------------------------------------------------------- proc_vga_start: process (rst, vga_clk) @@ -173,7 +142,7 @@ begin scan_enable <= '0'; elsif rising_edge(vga_clk) then if vsync = '1' then - if fifo_empty = '0' then + if ctrl_scan_en = '1' then scan_enable <= '1'; else scan_enable <= '0'; @@ -185,17 +154,23 @@ begin proc_vga_color_out: process (rst, vga_clk) variable do_scan : std_logic; + variable color : color_t; begin if rst = '1' then do_scan := '0'; elsif rising_edge(vga_clk) then - vga_color_out <= (X"00", X"00", X"00"); + vga_red <= X"00"; + vga_green <= X"00"; + vga_blue <= X"00"; if do_scan = '1' then - if direct_draw_en = '1' then - vga_color_out <= direct_color_in; - else - vga_color_out <= color; - end if; + for i in 0 to VGA_NUM_CH-1 loop + color := color_in(i); + if color_en(i) = '1' then + vga_red <= color(r); -- ToDo: color_op over channels + vga_green <= color(g); -- ToDo: color_op over channels + vga_blue <= color(b); -- ToDo: color_op over channels + end if; + end loop; end if; do_scan := is_scan; end if;