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- reworked PISO and SIPO

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git-svn-id: http://moon:8086/svn/vhdl/trunk@1264 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2015-05-30 12:27:45 +00:00
parent 99b30ba0cc
commit 0e0a7e48a6
7 changed files with 185 additions and 142 deletions
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lib/emac/src/piso.vhd
+51 -28
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@@ -17,11 +17,11 @@ ENTITY piso IS
rst : in STD_LOGIC;
clk : in STD_LOGIC;
din_vld : in STD_LOGIC;
din_rdy : out STD_LOGIC;
din_be : in unsigned(data_width_in/data_width_out-1 downto 0);
din_re : out STD_LOGIC;
din : in unsigned(data_width_in-1 downto 0);
din_be : in unsigned(data_width_in/data_width_out-1 downto 0);
dout_vld : out STD_LOGIC;
dout_en : in STD_LOGIC;
shift_en : in STD_LOGIC;
dout : out unsigned(data_width_out-1 downto 0)
);
@@ -34,43 +34,66 @@ ARCHITECTURE behavior OF piso IS
signal shift_cnt_pipe : unsigned(num_shifts-1 downto 0);
signal shift_pipe : unsigned(data_width_in-1 downto 0);
signal vld_pipe : unsigned(num_shifts-1 downto 0);
signal din_reg : unsigned(data_width_in-1 downto 0);
signal din_be_reg : unsigned(num_shifts-1 downto 0);
signal din_reg_empty : STD_LOGIC;
signal shift_reg_we : STD_LOGIC;
type state_t is (idle, shift, finish);
signal state : state_t;
signal state_next : state_t;
--------------------------------------------------------------------------
begin
pre_fin <= shift_cnt_pipe(shift_cnt_pipe'left-1);
din_rdy <= din_reg_empty;
dout_vld <= vld_pipe(vld_pipe'left) when msb_first else vld_pipe(0);
dout <= shift_pipe(shift_pipe'left downto shift_pipe'left-data_width_out+1) when msb_first
else shift_pipe(data_width_out-1 downto 0);
--------------------------------------------------------------------------
proc_state_next:
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
din_reg_empty <= '1';
elsif din_reg_empty = '1' then
if din_vld = '1' then
din_reg_empty <= '0';
end if;
elsif pre_fin = '1' and dout_en = '1' then
din_reg_empty <= '1';
state <= idle;
else
state <= state_next;
end if;
end if;
end process;
process(clk)
proc_fsm:
process(state, din_vld, pre_fin)
begin
if rising_edge(clk) then
if din_vld = '1' and din_reg_empty = '1' then
din_reg <= din;
din_be_reg <= din_be;
state_next <= state;
shift_reg_we <= '0';
din_re <= '0';
case state is
when idle =>
din_re <= '1';
if din_vld = '1' then
shift_reg_we <= '1';
state_next <= shift;
end if;
end if;
when shift =>
if pre_fin = '1' then
din_re <= din_vld;
if din_vld = '1' then
shift_reg_we <= '1';
state_next <= shift;
else
state_next <= idle;
end if;
end if;
when finish =>
state_next <= idle;
when others =>
state_next <= idle;
end case;
end process;
process(clk)
@@ -78,9 +101,9 @@ begin
if rising_edge(clk) then
if rst = '1' then
shift_cnt_pipe <= (others => '1');
elsif (pre_fin = '1' and dout_en = '1' and din_reg_empty = '0') then
elsif shift_reg_we = '1' then
shift_cnt_pipe <= (others => '0');
elsif dout_en = '1' then
elsif shift_en = '1' then
shift_cnt_pipe <= shift_cnt_pipe(shift_cnt_pipe'left-1 downto 0) & '1';
end if;
end if;
@@ -90,9 +113,9 @@ end process;
process(clk)
begin
if rising_edge(clk) then
if (pre_fin = '1' and dout_en = '1' and din_reg_empty = '0') then
shift_pipe <= din_reg;
elsif dout_en = '1' then
if shift_reg_we = '1' then
shift_pipe <= din;
elsif shift_en = '1' then
if (msb_first) then
shift_pipe <= shift_pipe(shift_pipe'left-data_width_out downto 0) & (data_width_out-1 downto 0 => '0');
else
@@ -108,9 +131,9 @@ begin
if rising_edge(clk) then
if rst = '1' then
vld_pipe <= (others => '0');
elsif (pre_fin = '1' and dout_en = '1' and din_reg_empty = '0') then
vld_pipe <= din_be_reg;
elsif dout_en = '1' then
elsif shift_reg_we = '1' then
vld_pipe <= din_be;
elsif shift_en = '1' then
if (msb_first) then
vld_pipe <= vld_pipe(vld_pipe'left-1 downto 0) & '0';
else