diff --git a/lib/emac/sim/tb_emac_top_jb.wdo b/lib/emac/sim/tb_emac_top_jb.wdo index 5953624..4832ca1 100644 --- a/lib/emac/sim/tb_emac_top_jb.wdo +++ b/lib/emac/sim/tb_emac_top_jb.wdo @@ -90,13 +90,13 @@ add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/s add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo32_dout add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo32_dout_be add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo32_dout_vld -add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo32_dout_en +add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo32_shift_en add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo32_en add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo32_rst add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo8_dout add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo8_rst add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo8_dout_vld -add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo8_dout_en +add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo8_shift_en add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/host_s add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/xfer_s add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/preamble_bsy @@ -157,11 +157,12 @@ add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_ add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ram_dout_b add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso32_din add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso32_din_be -add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso32_din_rdy +add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso32_din_re add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso32_din_vld add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso32_dout add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso32_dout_vld -add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso32_dout_en +add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso32_shift_en +add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/inst_piso32/state add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mii_fifo_we add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mii_fifo_re add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mii_fifo_full @@ -170,8 +171,9 @@ add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso8_din_vld add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso8_din add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso8_dout_vld -add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso8_din_rdy +add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso8_din_re add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso8_dout +add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/inst_piso8/state add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fcs_rst add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fcs_en add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fcs_din_vld @@ -186,7 +188,7 @@ add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mem_free_req add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mem_free_ack TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {242561800 ps} 0} {{Cursor 2} {49999967706 ps} 0} {{Cursor 3} {33469645300 ps} 0} {{Cursor 4} {10461894403 ps} 0} {{Cursor 5} {4181100 ps} 0} +WaveRestoreCursors {{Cursor 1} {2554530201 ps} 0} {{Cursor 2} {49999967706 ps} 0} {{Cursor 3} {33469645300 ps} 0} {{Cursor 4} {10461894403 ps} 0} {{Cursor 5} {1008401396 ps} 0} configure wave -namecolwidth 150 configure wave -valuecolwidth 100 configure wave -justifyvalue left @@ -200,4 +202,4 @@ configure wave -gridperiod 100 configure wave -griddelta 40 configure wave -timeline 1 update -WaveRestoreZoom {0 ps} {52500 us} +WaveRestoreZoom {1008142925 ps} {1009327916 ps} diff --git a/lib/emac/sim/tb_serdes.wdo b/lib/emac/sim/tb_serdes.wdo index 6137fb4..6f32682 100644 --- a/lib/emac/sim/tb_serdes.wdo +++ b/lib/emac/sim/tb_serdes.wdo @@ -1,58 +1,76 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Logic /tb_serdes/clk -add wave -noupdate -format Logic /tb_serdes/rst -add wave -noupdate -divider PiSo -add wave -noupdate -format Logic /tb_serdes/clk -add wave -noupdate -format Logic /tb_serdes/piso_din_vld -add wave -noupdate -format Logic /tb_serdes/piso_din_rdy -add wave -noupdate -format Literal /tb_serdes/piso_din_be -add wave -noupdate -format Literal -radix hexadecimal /tb_serdes/piso_din -add wave -noupdate -format Logic /tb_serdes/piso_dout_vld -add wave -noupdate -format Literal -radix hexadecimal /tb_serdes/piso_dout -add wave -noupdate -format Logic /tb_serdes/piso_dout_en -add wave -noupdate -divider SiPo -add wave -noupdate -format Logic /tb_serdes/clk -add wave -noupdate -format Logic /tb_serdes/sipo_enable -add wave -noupdate -format Logic /tb_serdes/sipo_rst -add wave -noupdate -format Logic /tb_serdes/sipo_din_vld -add wave -noupdate -format Literal -radix hexadecimal /tb_serdes/sipo_din -add wave -noupdate -format Logic /tb_serdes/sipo_dout_vld -add wave -noupdate -format Logic /tb_serdes/sipo_dout_en -add wave -noupdate -format Literal /tb_serdes/sipo_dout_be -add wave -noupdate -format Literal -radix hexadecimal /tb_serdes/sipo_dout -add wave -noupdate -divider PiSo -add wave -noupdate -format Logic /tb_serdes/clk -add wave -noupdate -format Logic /tb_serdes/piso2_din_vld -add wave -noupdate -format Logic /tb_serdes/piso2_din_rdy -add wave -noupdate -format Literal /tb_serdes/piso2_din_be -add wave -noupdate -format Literal -radix hexadecimal /tb_serdes/piso2_din -add wave -noupdate -format Logic /tb_serdes/piso2_dout_vld -add wave -noupdate -format Literal -radix hexadecimal /tb_serdes/piso2_dout -add wave -noupdate -format Logic /tb_serdes/piso2_dout_en -add wave -noupdate -divider SiPo -add wave -noupdate -format Logic /tb_serdes/clk -add wave -noupdate -format Logic /tb_serdes/sipo2_enable -add wave -noupdate -format Logic /tb_serdes/sipo2_rst -add wave -noupdate -format Logic /tb_serdes/sipo2_din_vld -add wave -noupdate -format Literal -radix hexadecimal /tb_serdes/sipo2_din -add wave -noupdate -format Logic /tb_serdes/sipo2_dout_vld -add wave -noupdate -format Logic /tb_serdes/sipo2_dout_en -add wave -noupdate -format Literal /tb_serdes/sipo2_dout_be -add wave -noupdate -format Literal -radix hexadecimal /tb_serdes/sipo2_dout -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {19757882 ps} 0} {{Cursor 2} {49999912163 ps} 0} {{Cursor 3} {49999529250 ps} 0} -configure wave -namecolwidth 150 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 100 -configure wave -griddelta 40 -configure wave -timeline 1 -update -WaveRestoreZoom {0 ps} {21 us} +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate -format Logic /tb_serdes/clk +add wave -noupdate -format Logic /tb_serdes/rst +add wave -noupdate -divider PiSo +add wave -noupdate -format Logic /tb_serdes/clk +add wave -noupdate -format Logic /tb_serdes/piso_din_vld +add wave -noupdate -format Logic /tb_serdes/piso_din_re +add wave -noupdate -format Literal /tb_serdes/piso_din_be +add wave -noupdate -format Literal -radix hexadecimal /tb_serdes/piso_din +add wave -noupdate -format Logic /tb_serdes/piso_dout_vld +add wave -noupdate -format Literal -radix hexadecimal /tb_serdes/piso_dout +add wave -noupdate -format Logic /tb_serdes/piso_shift_en +add wave -noupdate -divider {PiSo Int.} +add wave -noupdate -format Literal /tb_serdes/inst_piso/data_width_in +add wave -noupdate -format Literal /tb_serdes/inst_piso/data_width_out +add wave -noupdate -format Logic /tb_serdes/inst_piso/msb_first +add wave -noupdate -format Logic /tb_serdes/inst_piso/rst +add wave -noupdate -format Logic /tb_serdes/inst_piso/clk +add wave -noupdate -format Logic /tb_serdes/inst_piso/din_vld +add wave -noupdate -format Logic /tb_serdes/inst_piso/din_re +add wave -noupdate -format Literal /tb_serdes/inst_piso/din_be +add wave -noupdate -format Literal -radix hexadecimal /tb_serdes/inst_piso/din +add wave -noupdate -format Logic /tb_serdes/inst_piso/dout_vld +add wave -noupdate -format Logic /tb_serdes/inst_piso/shift_en +add wave -noupdate -format Literal -radix hexadecimal /tb_serdes/inst_piso/dout +add wave -noupdate -format Logic /tb_serdes/inst_piso/pre_fin +add wave -noupdate -format Literal /tb_serdes/inst_piso/shift_cnt_pipe +add wave -noupdate -format Literal -radix hexadecimal /tb_serdes/inst_piso/shift_pipe +add wave -noupdate -format Literal /tb_serdes/inst_piso/vld_pipe +add wave -noupdate -format Literal /tb_serdes/inst_piso/state +add wave -noupdate -divider SiPo +add wave -noupdate -format Logic /tb_serdes/clk +add wave -noupdate -format Logic /tb_serdes/sipo_enable +add wave -noupdate -format Logic /tb_serdes/sipo_rst +add wave -noupdate -format Logic /tb_serdes/sipo_din_vld +add wave -noupdate -format Literal -radix hexadecimal /tb_serdes/sipo_din +add wave -noupdate -format Logic /tb_serdes/sipo_dout_vld +add wave -noupdate -format Logic /tb_serdes/sipo_shift_en +add wave -noupdate -format Literal /tb_serdes/sipo_dout_be +add wave -noupdate -format Literal -radix hexadecimal /tb_serdes/sipo_dout +add wave -noupdate -divider PiSo +add wave -noupdate -format Logic /tb_serdes/clk +add wave -noupdate -format Logic /tb_serdes/piso2_din_vld +add wave -noupdate -format Logic /tb_serdes/piso2_din_re +add wave -noupdate -format Literal /tb_serdes/piso2_din_be +add wave -noupdate -format Literal -radix hexadecimal /tb_serdes/piso2_din +add wave -noupdate -format Logic /tb_serdes/piso2_dout_vld +add wave -noupdate -format Literal -radix hexadecimal /tb_serdes/piso2_dout +add wave -noupdate -format Logic /tb_serdes/piso2_shift_en +add wave -noupdate -divider SiPo +add wave -noupdate -format Logic /tb_serdes/clk +add wave -noupdate -format Logic /tb_serdes/sipo2_enable +add wave -noupdate -format Logic /tb_serdes/sipo2_rst +add wave -noupdate -format Logic /tb_serdes/sipo2_din_vld +add wave -noupdate -format Literal -radix hexadecimal /tb_serdes/sipo2_din +add wave -noupdate -format Logic /tb_serdes/sipo2_dout_vld +add wave -noupdate -format Logic /tb_serdes/sipo2_shift_en +add wave -noupdate -format Literal /tb_serdes/sipo2_dout_be +add wave -noupdate -format Literal -radix hexadecimal /tb_serdes/sipo2_dout +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {6620000 ps} 0} {{Cursor 2} {49999912163 ps} 0} {{Cursor 3} {49999529250 ps} 0} +configure wave -namecolwidth 150 +configure wave -valuecolwidth 100 +configure wave -justifyvalue left +configure wave -signalnamewidth 1 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 100 +configure wave -griddelta 40 +configure wave -timeline 1 +update +WaveRestoreZoom {0 ps} {21 us} diff --git a/lib/emac/src/emac_rx.vhd b/lib/emac/src/emac_rx.vhd index 365e3b5..2ad5020 100644 --- a/lib/emac/src/emac_rx.vhd +++ b/lib/emac/src/emac_rx.vhd @@ -73,14 +73,14 @@ ARCHITECTURE behavior OF emac_rx IS signal sipo32_dout : unsigned(31 downto 0); signal sipo32_dout_be : unsigned(3 downto 0); signal sipo32_dout_vld : std_logic; - signal sipo32_dout_en : std_logic; + signal sipo32_shift_en : std_logic; signal sipo32_en : std_logic; signal sipo32_rst : std_logic; signal sipo8_dout : unsigned(7 downto 0); signal sipo8_rst : std_logic; signal sipo8_dout_vld : std_logic; - signal sipo8_dout_en : std_logic; + signal sipo8_shift_en : std_logic; signal sipo8_en : std_logic; signal byte_count_rst : std_logic; @@ -349,7 +349,7 @@ xfer_state_next: end process; xfer_state: - process(xfer_s, rx_en, sipo32_dout_en, preamble_bsy, preamble_OK, xfer_ram_full) + process(xfer_s, rx_en, sipo32_shift_en, preamble_bsy, preamble_OK, xfer_ram_full) begin commit_en <= '0'; @@ -390,11 +390,11 @@ xfer_state: when xfer_setup => xfer_set <= '1'; sipo32_en <= rx_en; - xfer_en <= sipo32_dout_en; + xfer_en <= sipo32_shift_en; xfer_sn <= xfer_active; when xfer_active => - xfer_en <= sipo32_dout_en; + xfer_en <= sipo32_shift_en; sipo32_en <= rx_en; if xfer_ram_full = '1' then xfer_sn <= xfer_init; @@ -403,8 +403,8 @@ xfer_state: end if; when xfer_finish => - xfer_en <= sipo32_dout_en; - if sipo32_dout_en = '0' then + xfer_en <= sipo32_shift_en; + if sipo32_shift_en = '0' then xfer_sn <= xfer_commit; end if; @@ -477,7 +477,7 @@ inst_sipo32 : entity work.sipo dout_be => sipo32_dout_be, dout_vld => sipo32_dout_vld, dout => sipo32_dout, - dout_en => sipo32_dout_en + shift_en => sipo32_shift_en ); @@ -524,7 +524,7 @@ mii_input_register: else sipo32_din <= sipo8_dout; sipo32_din_vld <= sipo8_dout_vld; - rx_en <= sipo8_dout_en; + rx_en <= sipo8_shift_en; end if; end if; end process; @@ -546,11 +546,11 @@ inst_sipo_8bit : entity work.sipo dout_be => open, dout_vld => sipo8_dout_vld, dout => sipo8_dout, - dout_en => sipo8_dout_en + shift_en => sipo8_shift_en ); - sipo8_rst <= reset_en or not (mii_rx_dv or sipo8_dout_en); + sipo8_rst <= reset_en or not (mii_rx_dv or sipo8_shift_en); sipo8_en <= not mii_rx_er; end behavior; diff --git a/lib/emac/src/emac_tx.vhd b/lib/emac/src/emac_tx.vhd index fae7dfc..219f9ee 100644 --- a/lib/emac/src/emac_tx.vhd +++ b/lib/emac/src/emac_tx.vhd @@ -85,15 +85,15 @@ ARCHITECTURE behavior OF emac_tx IS signal piso32_din : unsigned(31 downto 0); signal piso32_din_be : unsigned(3 downto 0); - signal piso32_din_rdy : std_logic; + signal piso32_din_re : std_logic; signal piso32_din_vld : std_logic; signal piso32_dout : unsigned(7 downto 0); signal piso32_dout_vld : std_logic; - signal piso32_dout_en : std_logic; + signal piso32_shift_en : std_logic; signal piso8_dout_vld : std_logic; - signal piso8_din_rdy : std_logic; + signal piso8_din_re : std_logic; signal piso8_din_vld : std_logic; signal piso8_dout : unsigned(3 downto 0); signal piso8_din : unsigned(7 downto 0); @@ -164,7 +164,7 @@ begin reset_en <= reset_pipe(reset_pipe'left); - xfer_cnt_en <= xfer_bsy and piso32_din_rdy; + xfer_cnt_en <= xfer_bsy and piso32_din_re; fill_cnt_en <= fill_bsy and din_vld; mem_free_en <= not mem_free_ack(0) and mem_free_ack(1); @@ -475,7 +475,7 @@ xfer_state_next: end process; xfer_state: - process(xfer_s, mii_bsy, cmd_fifo_empty, piso32_din_rdy, piso32_dout_vld, xfer_bsy, fcs_gen_en) + process(xfer_s, mii_bsy, cmd_fifo_empty, piso32_din_re, piso32_dout_vld, xfer_bsy, fcs_gen_en) begin piso32_din_vld <= '0'; @@ -511,7 +511,7 @@ xfer_state: preamble_addr <= 0; preamble_en <= '1'; piso32_din_vld <= '1'; - if piso32_din_rdy = '1' then + if piso32_din_re = '1' then xfer_sn <= xfer_preamble1; end if; @@ -519,7 +519,7 @@ xfer_state: preamble_addr <= 1; preamble_en <= '1'; piso32_din_vld <= '1'; - if piso32_din_rdy = '1' then + if piso32_din_re = '1' then xfer_sn <= xfer_active; xfer_en <= '1'; end if; @@ -540,9 +540,9 @@ xfer_state: end if; when xfer_crc => - fcs_inject_en <= piso32_din_rdy; + fcs_inject_en <= piso32_din_re; piso32_din_vld <= '1'; - if piso32_din_rdy = '1' then + if piso32_din_re = '1' then xfer_sn <= xfer_finish; end if; @@ -569,7 +569,7 @@ inst_ram : entity work.dpram_1w1r2c_ro clk_a => clk, clk_b => mii_tx_clk, we_a => ram_we_a, - re_b => piso32_din_rdy, + re_b => piso32_din_re, addr_a => ram_addr_a, addr_b => ram_addr_b, din_a => ram_din_a, @@ -613,16 +613,16 @@ inst_piso32 : entity work.piso rst => reset_en, clk => mii_tx_clk, din_vld => piso32_din_vld, - din_rdy => piso32_din_rdy, + din_re => piso32_din_re, din_be => piso32_din_be, din => piso32_din, dout_vld => piso32_dout_vld, - dout_en => piso32_dout_en, + shift_en => piso32_shift_en, dout => piso32_dout ); - piso32_dout_en <= not mii_fifo_full; --'1' when Gbps_en = '1' else piso8_din_rdy; + piso32_shift_en <= not mii_fifo_full; --'1' when Gbps_en = '1' else piso8_din_re; ------------------------------------------------------------------ fcs_enable_gen: @@ -654,7 +654,7 @@ inst_fcs: entity work.crc32 ); - fcs_din_vld <= fcs_en(fcs_en'left) and piso32_dout_vld and piso32_dout_en; + fcs_din_vld <= fcs_en(fcs_en'left) and piso32_dout_vld and piso32_shift_en; ------------------------------------------------------------------ -- ensures continous MII-data stream and also acts as Inter Frame Gap delay @@ -699,7 +699,7 @@ inst_mii_fifo: entity work.fifo_sync data_r => piso8_din ); - mii_fifo_re <= mii_bsy when Gbps_en = '1' else (piso8_din_rdy and mii_bsy); + mii_fifo_re <= mii_bsy when Gbps_en = '1' else (piso8_din_re and mii_bsy); mii_fifo_we <= piso32_dout_vld; ------------------------------------------------------------------ @@ -715,11 +715,11 @@ inst_piso8 : entity work.piso rst => reset_en, clk => mii_tx_clk, din_vld => piso8_din_vld, - din_rdy => piso8_din_rdy, + din_re => piso8_din_re, din_be => "11", din => piso8_din, dout_vld => piso8_dout_vld, - dout_en => '1', + shift_en => '1', dout => piso8_dout ); diff --git a/lib/emac/src/piso.vhd b/lib/emac/src/piso.vhd index 1c27e8d..966e769 100644 --- a/lib/emac/src/piso.vhd +++ b/lib/emac/src/piso.vhd @@ -17,11 +17,11 @@ ENTITY piso IS rst : in STD_LOGIC; clk : in STD_LOGIC; din_vld : in STD_LOGIC; - din_rdy : out STD_LOGIC; - din_be : in unsigned(data_width_in/data_width_out-1 downto 0); + din_re : out STD_LOGIC; din : in unsigned(data_width_in-1 downto 0); + din_be : in unsigned(data_width_in/data_width_out-1 downto 0); dout_vld : out STD_LOGIC; - dout_en : in STD_LOGIC; + shift_en : in STD_LOGIC; dout : out unsigned(data_width_out-1 downto 0) ); @@ -34,43 +34,66 @@ ARCHITECTURE behavior OF piso IS signal shift_cnt_pipe : unsigned(num_shifts-1 downto 0); signal shift_pipe : unsigned(data_width_in-1 downto 0); signal vld_pipe : unsigned(num_shifts-1 downto 0); - signal din_reg : unsigned(data_width_in-1 downto 0); - signal din_be_reg : unsigned(num_shifts-1 downto 0); - signal din_reg_empty : STD_LOGIC; + signal shift_reg_we : STD_LOGIC; + + type state_t is (idle, shift, finish); + signal state : state_t; + signal state_next : state_t; -------------------------------------------------------------------------- begin pre_fin <= shift_cnt_pipe(shift_cnt_pipe'left-1); - din_rdy <= din_reg_empty; dout_vld <= vld_pipe(vld_pipe'left) when msb_first else vld_pipe(0); dout <= shift_pipe(shift_pipe'left downto shift_pipe'left-data_width_out+1) when msb_first else shift_pipe(data_width_out-1 downto 0); -------------------------------------------------------------------------- +proc_state_next: process(clk) begin if rising_edge(clk) then if rst = '1' then - din_reg_empty <= '1'; - elsif din_reg_empty = '1' then - if din_vld = '1' then - din_reg_empty <= '0'; - end if; - elsif pre_fin = '1' and dout_en = '1' then - din_reg_empty <= '1'; + state <= idle; + else + state <= state_next; end if; end if; end process; -process(clk) +proc_fsm: +process(state, din_vld, pre_fin) begin - if rising_edge(clk) then - if din_vld = '1' and din_reg_empty = '1' then - din_reg <= din; - din_be_reg <= din_be; + state_next <= state; + shift_reg_we <= '0'; + din_re <= '0'; + case state is + + when idle => + din_re <= '1'; + if din_vld = '1' then + shift_reg_we <= '1'; + state_next <= shift; end if; - end if; + + when shift => + if pre_fin = '1' then + din_re <= din_vld; + if din_vld = '1' then + shift_reg_we <= '1'; + state_next <= shift; + else + state_next <= idle; + end if; + end if; + + when finish => + state_next <= idle; + + when others => + state_next <= idle; + + end case; end process; process(clk) @@ -78,9 +101,9 @@ begin if rising_edge(clk) then if rst = '1' then shift_cnt_pipe <= (others => '1'); - elsif (pre_fin = '1' and dout_en = '1' and din_reg_empty = '0') then + elsif shift_reg_we = '1' then shift_cnt_pipe <= (others => '0'); - elsif dout_en = '1' then + elsif shift_en = '1' then shift_cnt_pipe <= shift_cnt_pipe(shift_cnt_pipe'left-1 downto 0) & '1'; end if; end if; @@ -90,9 +113,9 @@ end process; process(clk) begin if rising_edge(clk) then - if (pre_fin = '1' and dout_en = '1' and din_reg_empty = '0') then - shift_pipe <= din_reg; - elsif dout_en = '1' then + if shift_reg_we = '1' then + shift_pipe <= din; + elsif shift_en = '1' then if (msb_first) then shift_pipe <= shift_pipe(shift_pipe'left-data_width_out downto 0) & (data_width_out-1 downto 0 => '0'); else @@ -108,9 +131,9 @@ begin if rising_edge(clk) then if rst = '1' then vld_pipe <= (others => '0'); - elsif (pre_fin = '1' and dout_en = '1' and din_reg_empty = '0') then - vld_pipe <= din_be_reg; - elsif dout_en = '1' then + elsif shift_reg_we = '1' then + vld_pipe <= din_be; + elsif shift_en = '1' then if (msb_first) then vld_pipe <= vld_pipe(vld_pipe'left-1 downto 0) & '0'; else diff --git a/lib/emac/src/sipo.vhd b/lib/emac/src/sipo.vhd index 03c1005..48c2a1e 100644 --- a/lib/emac/src/sipo.vhd +++ b/lib/emac/src/sipo.vhd @@ -19,7 +19,7 @@ ENTITY sipo IS din_en : in STD_LOGIC; din_vld : in STD_LOGIC; din : in unsigned(data_width_in-1 downto 0); - dout_en : out STD_LOGIC; + shift_en : out STD_LOGIC; dout_vld : out STD_LOGIC; dout : out unsigned(data_width_out-1 downto 0); dout_be : out unsigned(data_width_out/data_width_in-1 downto 0) @@ -42,7 +42,7 @@ ARCHITECTURE behavior OF sipo IS begin pre_fin <= shift_cnt_pipe(shift_cnt_pipe'left) when msb_first else shift_cnt_pipe(0); - dout_en <= out_en; + shift_en <= out_en; dout_vld <= out_vld; -------------------------------------------------------------------------- diff --git a/lib/emac/src/tb_serdes.vhd b/lib/emac/src/tb_serdes.vhd index 1f16310..8ad5cd1 100644 --- a/lib/emac/src/tb_serdes.vhd +++ b/lib/emac/src/tb_serdes.vhd @@ -37,27 +37,27 @@ ARCHITECTURE behavior OF tb_serdes IS signal RST : std_logic := '1'; signal piso_din_vld : std_logic := '0'; - signal piso_din_rdy : std_logic; + signal piso_din_re : std_logic; signal piso_din_be : unsigned(3 downto 0) := (others => '0'); signal piso_din : unsigned(31 downto 0) := (others => '-'); signal piso_dout_vld : std_logic; signal piso_dout : unsigned(7 downto 0); - signal piso_dout_en : std_logic; + signal piso_shift_en : std_logic; signal piso2_din_vld : std_logic := '0'; - signal piso2_din_rdy : std_logic; + signal piso2_din_re : std_logic; signal piso2_din_be : unsigned(1 downto 0) := (others => '1'); signal piso2_din : unsigned(7 downto 0) := (others => '-'); signal piso2_dout_vld : std_logic; signal piso2_dout : unsigned(3 downto 0); - signal piso2_dout_en : std_logic; + signal piso2_shift_en : std_logic; signal sipo_enable : std_logic := '0'; signal sipo_rst : std_logic := '0'; signal sipo_din_vld : std_logic := '0'; signal sipo_din : unsigned(7 downto 0) := (others => '-'); signal sipo_dout_vld : std_logic; - signal sipo_dout_en : std_logic; + signal sipo_shift_en : std_logic; signal sipo_dout_be : unsigned(3 downto 0); signal sipo_dout : unsigned(31 downto 0); @@ -66,7 +66,7 @@ ARCHITECTURE behavior OF tb_serdes IS signal sipo2_din_vld : std_logic := '0'; signal sipo2_din : unsigned(3 downto 0) := (others => '-'); signal sipo2_dout_vld : std_logic; - signal sipo2_dout_en : std_logic; + signal sipo2_shift_en : std_logic; signal sipo2_dout_be : unsigned(1 downto 0); signal sipo2_dout : unsigned(7 downto 0); @@ -85,16 +85,16 @@ inst_piso : entity work.piso rst => RST, clk => CLK, din_vld => piso_din_vld, - din_rdy => piso_din_rdy, + din_re => piso_din_re, din_be => piso_din_be, din => piso_din, dout_vld => piso_dout_vld, - dout_en => piso_dout_en, + shift_en => piso_shift_en, dout => piso_dout ); - piso_dout_en <= piso2_din_rdy; + piso_shift_en <= piso2_din_re; inst_piso2 : entity work.piso GENERIC MAP @@ -108,17 +108,17 @@ inst_piso2 : entity work.piso rst => RST, clk => CLK, din_vld => piso2_din_vld, - din_rdy => piso2_din_rdy, + din_re => piso2_din_re, din_be => piso2_din_be, din => piso2_din, dout_vld => piso2_dout_vld, - dout_en => piso2_dout_en, + shift_en => piso2_shift_en, dout => piso2_dout ); piso2_din_vld <= piso_dout_vld; - piso2_dout_en <= '1'; + piso2_shift_en <= '1'; piso2_din <= piso_dout; inst_sipo : entity work.sipo @@ -138,12 +138,12 @@ inst_sipo : entity work.sipo dout_be => sipo_dout_be, dout_vld => sipo_dout_vld, dout => sipo_dout, - dout_en => sipo_dout_en + shift_en => sipo_shift_en ); sipo_din <= sipo2_dout; sipo_din_vld <= sipo2_dout_vld; - sipo_enable <= sipo2_dout_en; + sipo_enable <= sipo2_shift_en; sipo_rst <= RST or not piso2_dout_vld; inst_sipo2 : entity work.sipo @@ -163,7 +163,7 @@ inst_sipo2 : entity work.sipo dout_be => sipo2_dout_be, dout_vld => sipo2_dout_vld, dout => sipo2_dout, - dout_en => sipo2_dout_en + shift_en => sipo2_shift_en ); sipo2_din <= piso2_dout; @@ -194,16 +194,16 @@ STIMULUS: process piso_din_vld <= '1'; piso_din <= X"12345678"; piso_din_be <= "1111"; - wait until rising_edge(CLK) and piso_din_rdy = '1'; + wait until rising_edge(CLK) and piso_din_re = '1'; piso_din <= piso_din + X"12345678"; piso_din_be <= "1111"; - wait until rising_edge(CLK) and piso_din_rdy = '1'; + wait until rising_edge(CLK) and piso_din_re = '1'; piso_din <= piso_din + X"12345678"; piso_din_be <= "1111"; - wait until rising_edge(CLK) and piso_din_rdy = '1'; + wait until rising_edge(CLK) and piso_din_re = '1'; piso_din <= piso_din + X"12345678"; piso_din_be <= "1100"; - wait until rising_edge(CLK) and piso_din_rdy = '1'; + wait until rising_edge(CLK) and piso_din_re = '1'; piso_din <= (others => '-'); piso_din_vld <= '0';