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- reworked PISO and SIPO

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git-svn-id: http://moon:8086/svn/vhdl/trunk@1264 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2015-05-30 12:27:45 +00:00
parent 99b30ba0cc
commit 0e0a7e48a6
7 changed files with 185 additions and 142 deletions
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lib/emac/src/emac_tx.vhd
+17 -17
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@@ -85,15 +85,15 @@ ARCHITECTURE behavior OF emac_tx IS
signal piso32_din : unsigned(31 downto 0);
signal piso32_din_be : unsigned(3 downto 0);
signal piso32_din_rdy : std_logic;
signal piso32_din_re : std_logic;
signal piso32_din_vld : std_logic;
signal piso32_dout : unsigned(7 downto 0);
signal piso32_dout_vld : std_logic;
signal piso32_dout_en : std_logic;
signal piso32_shift_en : std_logic;
signal piso8_dout_vld : std_logic;
signal piso8_din_rdy : std_logic;
signal piso8_din_re : std_logic;
signal piso8_din_vld : std_logic;
signal piso8_dout : unsigned(3 downto 0);
signal piso8_din : unsigned(7 downto 0);
@@ -164,7 +164,7 @@ begin
reset_en <= reset_pipe(reset_pipe'left);
xfer_cnt_en <= xfer_bsy and piso32_din_rdy;
xfer_cnt_en <= xfer_bsy and piso32_din_re;
fill_cnt_en <= fill_bsy and din_vld;
mem_free_en <= not mem_free_ack(0) and mem_free_ack(1);
@@ -475,7 +475,7 @@ xfer_state_next:
end process;
xfer_state:
process(xfer_s, mii_bsy, cmd_fifo_empty, piso32_din_rdy, piso32_dout_vld, xfer_bsy, fcs_gen_en)
process(xfer_s, mii_bsy, cmd_fifo_empty, piso32_din_re, piso32_dout_vld, xfer_bsy, fcs_gen_en)
begin
piso32_din_vld <= '0';
@@ -511,7 +511,7 @@ xfer_state:
preamble_addr <= 0;
preamble_en <= '1';
piso32_din_vld <= '1';
if piso32_din_rdy = '1' then
if piso32_din_re = '1' then
xfer_sn <= xfer_preamble1;
end if;
@@ -519,7 +519,7 @@ xfer_state:
preamble_addr <= 1;
preamble_en <= '1';
piso32_din_vld <= '1';
if piso32_din_rdy = '1' then
if piso32_din_re = '1' then
xfer_sn <= xfer_active;
xfer_en <= '1';
end if;
@@ -540,9 +540,9 @@ xfer_state:
end if;
when xfer_crc =>
fcs_inject_en <= piso32_din_rdy;
fcs_inject_en <= piso32_din_re;
piso32_din_vld <= '1';
if piso32_din_rdy = '1' then
if piso32_din_re = '1' then
xfer_sn <= xfer_finish;
end if;
@@ -569,7 +569,7 @@ inst_ram : entity work.dpram_1w1r2c_ro
clk_a => clk,
clk_b => mii_tx_clk,
we_a => ram_we_a,
re_b => piso32_din_rdy,
re_b => piso32_din_re,
addr_a => ram_addr_a,
addr_b => ram_addr_b,
din_a => ram_din_a,
@@ -613,16 +613,16 @@ inst_piso32 : entity work.piso
rst => reset_en,
clk => mii_tx_clk,
din_vld => piso32_din_vld,
din_rdy => piso32_din_rdy,
din_re => piso32_din_re,
din_be => piso32_din_be,
din => piso32_din,
dout_vld => piso32_dout_vld,
dout_en => piso32_dout_en,
shift_en => piso32_shift_en,
dout => piso32_dout
);
piso32_dout_en <= not mii_fifo_full; --'1' when Gbps_en = '1' else piso8_din_rdy;
piso32_shift_en <= not mii_fifo_full; --'1' when Gbps_en = '1' else piso8_din_re;
------------------------------------------------------------------
fcs_enable_gen:
@@ -654,7 +654,7 @@ inst_fcs: entity work.crc32
);
fcs_din_vld <= fcs_en(fcs_en'left) and piso32_dout_vld and piso32_dout_en;
fcs_din_vld <= fcs_en(fcs_en'left) and piso32_dout_vld and piso32_shift_en;
------------------------------------------------------------------
-- ensures continous MII-data stream and also acts as Inter Frame Gap delay
@@ -699,7 +699,7 @@ inst_mii_fifo: entity work.fifo_sync
data_r => piso8_din
);
mii_fifo_re <= mii_bsy when Gbps_en = '1' else (piso8_din_rdy and mii_bsy);
mii_fifo_re <= mii_bsy when Gbps_en = '1' else (piso8_din_re and mii_bsy);
mii_fifo_we <= piso32_dout_vld;
------------------------------------------------------------------
@@ -715,11 +715,11 @@ inst_piso8 : entity work.piso
rst => reset_en,
clk => mii_tx_clk,
din_vld => piso8_din_vld,
din_rdy => piso8_din_rdy,
din_re => piso8_din_re,
din_be => "11",
din => piso8_din,
dout_vld => piso8_dout_vld,
dout_en => '1',
shift_en => '1',
dout => piso8_dout
);