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- changed frequencies into MHz units (real data type)

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git-svn-id: http://moon:8086/svn/vhdl/trunk@734 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2010-02-09 07:50:27 +00:00
parent 385aa5e008
commit 0c50e933f8
19 changed files with 161 additions and 144 deletions
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lib/misc/async_port_wb.vhd
+21 -21
View File
@@ -1,5 +1,5 @@
-----------------------------------------------------------------------
-- $Header: /tmp/cvsroot/VHDL/lib/misc/async_port_wb.vhd,v 1.14 2010-02-07 15:42:47 Jens Exp $
-- $Header: /tmp/cvsroot/VHDL/lib/misc/async_port_wb.vhd,v 1.15 2010-02-09 07:46:19 Jens Exp $
-----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
@@ -10,10 +10,10 @@ use work.async_types.all;
entity async_port_wb is
Generic
(
f_sysclk_hz : natural := 100E6;
addr_width : natural := 32;
data_width : natural := 32;
byte_sel_width : natural := 4;
f_sysclk : real := 100.0;
addr_width : natural := 32;
data_width : natural := 32;
byte_sel_width : natural := 4;
async_timespec : async_timespec_t
);
Port
@@ -73,9 +73,9 @@ architecture Behavioral of async_port_wb is
------------------------------------------------------------------
begin
ASSERT to_cycles(async_timespec.T_pulse_rd, f_sysclk_hz) > 0 report "Read pulse length must be greater than zero!" severity failure;
ASSERT to_cycles(async_timespec.T_pulse_wr, f_sysclk_hz) > 0 report "Write pulse length must be greater than zero!" severity failure;
ASSERT (not async_timespec.can_page_rd OR (to_cycles(async_timespec.T_pulse_page_rd, f_sysclk_hz) > 1)) report "Read page pulse length must be greater than one!" severity failure;
ASSERT to_cycles(async_timespec.T_pulse_rd, f_sysclk) > 0 report "Read pulse length must be greater than zero!" severity failure;
ASSERT to_cycles(async_timespec.T_pulse_wr, f_sysclk) > 0 report "Write pulse length must be greater than zero!" severity failure;
ASSERT (not async_timespec.can_page_rd OR (to_cycles(async_timespec.T_pulse_page_rd, f_sysclk) > 1)) report "Read page pulse length must be greater than one!" severity failure;
SRDY_O <= CYC_I and rdyo;
en <= CYC_I and STB_I;
@@ -111,7 +111,7 @@ architecture Behavioral of async_port_wb is
process(s, cycle_cnt, en, WE_I, WE_I_r, do_page_read)
begin
cycle_reload <= to_cycles(async_timespec.T_pulse_rst, f_sysclk_hz);
cycle_reload <= to_cycles(async_timespec.T_pulse_rst, f_sysclk);
cc_rst <= '0';
as.rst <= '0';
as.cs <= '0';
@@ -139,17 +139,17 @@ architecture Behavioral of async_port_wb is
if en = '1' then
as.cs <= '1';
cc_rst <= '1';
if to_cycles(async_timespec.T_leadin, f_sysclk_hz) = 0 then
if to_cycles(async_timespec.T_leadin, f_sysclk) = 0 then
sn <= pulse;
if WE_I = '1' then
cycle_reload <= 0;
sn <= leadin; -- always lead-in for writes
else
cycle_reload <= to_cycles(async_timespec.T_pulse_rd, f_sysclk_hz) - 1;
cycle_reload <= to_cycles(async_timespec.T_pulse_rd, f_sysclk) - 1;
as.rd <= '1';
end if;
else
cycle_reload <= to_cycles(async_timespec.T_leadin, f_sysclk_hz) - 1;
cycle_reload <= to_cycles(async_timespec.T_leadin, f_sysclk) - 1;
sn <= leadin;
end if;
end if;
@@ -163,9 +163,9 @@ architecture Behavioral of async_port_wb is
cc_rst <= '1';
sn <= pulse;
if WE_I_r = '1' then
cycle_reload <= to_cycles(async_timespec.T_pulse_wr, f_sysclk_hz) - 1;
cycle_reload <= to_cycles(async_timespec.T_pulse_wr, f_sysclk) - 1;
else
cycle_reload <= to_cycles(async_timespec.T_pulse_rd, f_sysclk_hz) - 1;
cycle_reload <= to_cycles(async_timespec.T_pulse_rd, f_sysclk) - 1;
end if;
end if;
@@ -180,17 +180,17 @@ architecture Behavioral of async_port_wb is
ack <= not WE_I_r;
rdy <= do_page_read;
if en = '1' and do_page_read = '1' then
cycle_reload <= to_cycles(async_timespec.T_pulse_page_rd, f_sysclk_hz) - 1;
cycle_reload <= to_cycles(async_timespec.T_pulse_page_rd, f_sysclk) - 1;
sn <= pulse;
elsif to_cycles(async_timespec.T_leadout, f_sysclk_hz) = 0 then
if to_cycles(async_timespec.T_release, f_sysclk_hz) = 0 then
elsif to_cycles(async_timespec.T_leadout, f_sysclk) = 0 then
if to_cycles(async_timespec.T_release, f_sysclk) = 0 then
sn <= idle;
else
cycle_reload <= to_cycles(async_timespec.T_release, f_sysclk_hz) - 1;
cycle_reload <= to_cycles(async_timespec.T_release, f_sysclk) - 1;
sn <= release;
end if;
else
cycle_reload <= to_cycles(async_timespec.T_leadout, f_sysclk_hz) - 1;
cycle_reload <= to_cycles(async_timespec.T_leadout, f_sysclk) - 1;
sn <= leadout;
end if;
end if;
@@ -200,10 +200,10 @@ architecture Behavioral of async_port_wb is
as.drive_d <= WE_I_r;
if cycle_cnt = 0 then
cc_rst <= '1';
if to_cycles(async_timespec.T_release, f_sysclk_hz) = 0 then
if to_cycles(async_timespec.T_release, f_sysclk) = 0 then
sn <= idle;
else
cycle_reload <= to_cycles(async_timespec.T_release, f_sysclk_hz) - 1;
cycle_reload <= to_cycles(async_timespec.T_release, f_sysclk) - 1;
sn <= release;
end if;
end if;
lib/misc/async_types.vhd
+3 -3
View File
@@ -44,16 +44,16 @@ package async_types is
pol_rst : std_logic;
end record;
function to_cycles(T_ns : real; f_hz : natural) return natural;
function to_cycles(T_ns : real; f_Mhz : real) return natural;
end async_types;
package body async_types is
function to_cycles(T_ns : real; f_hz : natural) return natural is
function to_cycles(T_ns : real; f_Mhz : real) return natural is
begin
return natural(0.5 + 1.0E-9*T_ns*real(f_hz));
return natural(0.5 + 1.0E-3*T_ns*f_Mhz);
end to_cycles;
end async_types;
lib/misc/clockgen_virtex4.vhd
+5 -5
View File
@@ -33,9 +33,9 @@ use UNISIM.vcomponents.all;
entity clockgen is
generic
(
clk_in_freq_hz : integer := 100E6;
clk0_out_phaseshift : integer := 0;
clk1_out_phaseshift : integer := 0
clk_in_freq : real := 100.0;
clk0_out_phaseshift : integer := 0;
clk1_out_phaseshift : integer := 0
);
port
(
@@ -114,7 +114,7 @@ inst_DCM_BASE_0 : DCM_BASE
CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32
CLKFX_MULTIPLY => 4, -- Can be any integer from 2 to 32
CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => UTILS_PERIOD_NS(clk_in_freq_hz), -- Specify period of input clock in ns from 1.25 to 1000.00
CLKIN_PERIOD => UTILS_PERIOD_NS(clk_in_freq), -- Specify period of input clock in ns from 1.25 to 1000.00
CLKOUT_PHASE_SHIFT => "FIXED", -- Specify phase shift mode of NONE or FIXED
CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE or 1X
DCM_AUTOCALIBRATION => TRUE, -- DCM calibrartion circuitry TRUE/FALSE
@@ -150,7 +150,7 @@ inst_DCM_BASE_0 : DCM_BASE
CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32
CLKFX_MULTIPLY => 4, -- Can be any integer from 2 to 32
CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => UTILS_PERIOD_NS(clk_in_freq_hz), -- Specify period of input clock in ns from 1.25 to 1000.00
CLKIN_PERIOD => UTILS_PERIOD_NS(clk_in_freq), -- Specify period of input clock in ns from 1.25 to 1000.00
CLKOUT_PHASE_SHIFT => "FIXED", -- Specify phase shift mode of NONE or FIXED
CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE or 1X
DCM_AUTOCALIBRATION => TRUE, -- DCM calibrartion circuitry TRUE/FALSE
lib/misc/gpio_wb.vhd
+2 -2
View File
@@ -5,7 +5,7 @@ USE IEEE.NUMERIC_STD.ALL;
ENTITY gpio_wb IS
Generic
(
f_sysclk_hz : natural := 100E6
f_sysclk : real := 100.0
);
Port
(
@@ -34,7 +34,7 @@ END gpio_wb;
ARCHITECTURE behavior OF gpio_wb IS
constant num_timers : natural := 2;
constant ncycles_usec : natural := f_sysclk_hz/1E6;
constant ncycles_usec : natural := natural(f_sysclk + 0.5);
signal gpo0_reg : unsigned(31 downto 0);
signal gpo1_reg : unsigned(31 downto 0);
lib/misc/utils_pkg.vhd
+19 -19
View File
@@ -1,5 +1,5 @@
-----------------------------------------------------------------------
-- $Header: /tmp/cvsroot/VHDL/lib/misc/utils_pkg.vhd,v 1.3 2009-11-03 20:38:30 Jens Exp $
-- $Header: /tmp/cvsroot/VHDL/lib/misc/utils_pkg.vhd,v 1.4 2010-02-09 07:46:19 Jens Exp $
-----------------------------------------------------------------------
library IEEE;
@@ -18,9 +18,9 @@ package utils_pkg is
function NextExpBaseTwo(x : natural) return natural;
function GCD(a, b : natural) return natural;
function LCM(a, b : natural) return natural;
function UTILS_PERIOD_NS(f_in_hz : natural) return real;
function UTILS_FREQ_M(f_in_hz, f_out_hz : natural) return natural;
function UTILS_FREQ_D(f_in_hz, f_out_hz : natural) return natural;
function UTILS_PERIOD_NS(f_in_MHz : real) return real;
function UTILS_FREQ_M(f_in_MHz, f_out_MHz : real) return natural;
function UTILS_FREQ_D(f_in_MHz, f_out_MHz : real) return natural;
end utils_pkg;
@@ -74,21 +74,21 @@ package body utils_pkg is
end LCM;
function UTILS_PERIOD_NS(f_in_hz : natural) return real is
function UTILS_PERIOD_NS(f_in_MHz : real) return real is
begin
return 1.0E9/real(f_in_hz);
return 1.0E3/f_in_MHz;
end UTILS_PERIOD_NS;
function UTILS_FREQ_M(f_in_hz, f_out_hz : natural) return natural is
variable f_in_mhz : natural;
variable f_out_mhz : natural;
function UTILS_FREQ_M(f_in_MHz, f_out_MHz : real) return natural is
variable f_in_hz : natural;
variable f_out_hz : natural;
variable m : natural;
begin
f_in_mhz := f_in_hz/1E6;
f_out_mhz := f_out_hz/1E6;
m := f_out_mhz/GCD(f_in_mhz, f_out_mhz);
f_in_hz := natural(f_in_MHz*1.0E6);
f_out_hz := natural(f_out_MHz*1.0E6);
m := f_out_hz/GCD(f_in_hz, f_out_hz);
if m = 1 then
m := 2;
@@ -98,16 +98,16 @@ package body utils_pkg is
end UTILS_FREQ_M;
function UTILS_FREQ_D(f_in_hz, f_out_hz : natural) return natural is
variable f_in_mhz : natural;
variable f_out_mhz : natural;
function UTILS_FREQ_D(f_in_MHz, f_out_MHz : real) return natural is
variable f_in_hz : natural;
variable f_out_hz : natural;
variable m : natural;
variable d : natural;
begin
m := UTILS_FREQ_M(f_in_hz, f_out_hz);
f_in_mhz := f_in_hz/1E6;
f_out_mhz := f_out_hz/1E6;
d := m*f_in_mhz/f_out_mhz;
m := UTILS_FREQ_M(f_in_MHz, f_out_MHz);
f_in_hz := natural(f_in_MHz*1.0E6);
f_out_hz := natural(f_out_MHz*1.0E6);
d := m*f_in_hz/f_out_hz;
return d;