jens
0c50e933f8
Committed on the Free edition of March Hare Software CVSNT Server. Upgrade to CVS Suite for more features and support: http://march-hare.com/cvsnt/ git-svn-id: http://moon:8086/svn/vhdl/trunk@734 cc03376c-175c-47c8-b038-4cd826a8556b
326 lines
7.6 KiB
VHDL
326 lines
7.6 KiB
VHDL
LIBRARY IEEE;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE IEEE.NUMERIC_STD.ALL;
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ENTITY gpio_wb IS
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Generic
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(
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f_sysclk : real := 100.0
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);
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Port
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(
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CLK_I : in STD_LOGIC;
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RST_I : in STD_LOGIC;
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CYC_I : in STD_LOGIC;
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STB_I : in STD_LOGIC;
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SEL_I : in unsigned(3 downto 0);
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WE_I : in STD_LOGIC;
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ACK_O : out STD_LOGIC;
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SRDY_O : out STD_LOGIC;
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MRDY_I : in STD_LOGIC;
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ADDR_I : in unsigned(31 downto 0);
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DAT_I : in unsigned(31 downto 0);
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DAT_O : out unsigned(31 downto 0);
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INT_TIM_O : out STD_LOGIC;
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sys_gpo0 : out unsigned(31 downto 0);
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sys_gpo1 : out unsigned(31 downto 0);
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sys_gpi0 : in unsigned(31 downto 0);
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sys_gpi1 : in unsigned(31 downto 0)
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);
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END gpio_wb;
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ARCHITECTURE behavior OF gpio_wb IS
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constant num_timers : natural := 2;
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constant ncycles_usec : natural := natural(f_sysclk + 0.5);
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signal gpo0_reg : unsigned(31 downto 0);
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signal gpo1_reg : unsigned(31 downto 0);
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signal gpi0_reg : unsigned(31 downto 0);
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signal gpi1_reg : unsigned(31 downto 0);
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-- Signals to form an timer generating an interrupt every microsecond
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subtype tick_usec_t is natural range 0 to ncycles_usec-1;
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signal tick_usec : tick_usec_t;
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signal cnt_usec : unsigned(31 downto 0);
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signal cnt_sec : unsigned(31 downto 0);
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signal cnt_usec_preset : unsigned(31 downto 0);
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signal cnt_sec_preset : unsigned(31 downto 0);
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signal cnt_usec_en : std_logic;
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signal cnt_usec_we : std_logic;
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signal cnt_sec_en : std_logic;
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signal cnt_sec_we : std_logic;
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type timer_array_t is array (0 to num_timers-1) of unsigned(31 downto 0);
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signal timer_cnt : timer_array_t;
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signal timer_cmp : timer_array_t;
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signal timer_en : unsigned(0 to num_timers-1);
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signal timer_inten : unsigned(0 to num_timers-1);
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signal timer_irq : unsigned(0 to num_timers-1);
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signal timer_ovl : unsigned(0 to num_timers-1);
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signal timer_irq_ack : unsigned(0 to num_timers-1);
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signal timer_cnt_we : unsigned(0 to num_timers-1);
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signal timer_cmp_we : unsigned(0 to num_timers-1);
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signal reg_data_wr : unsigned(31 downto 0);
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begin
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SRDY_O <= CYC_I;
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tim_irq:
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process(timer_irq)
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variable irq : std_logic;
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begin
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irq := '0';
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for i in 0 to num_timers-1 loop
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irq := irq or timer_irq(i);
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end loop;
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INT_TIM_O <= irq;
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end process;
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------------------------------------------------------------------
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led_out:
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process(CLK_I)
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begin
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if rising_edge(CLK_I) then
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sys_gpo0 <= gpo0_reg;
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sys_gpo1 <= gpo1_reg;
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end if;
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end process;
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------------------------------------------------------------------
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btn_ps2_in:
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process(CLK_I)
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begin
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if rising_edge(CLK_I) then
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gpi0_reg <= sys_gpi0;
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gpi1_reg <= sys_gpi1;
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end if;
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end process;
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------------------------------------------------------------------
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registers_write:
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process(CLK_I)
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begin
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if rising_edge(CLK_I) then
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cnt_usec_we <= '0';
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cnt_sec_we <= '0';
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timer_cnt_we <= (others => '0');
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timer_cmp_we <= (others => '0');
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timer_irq_ack <= (others => '0');
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if RST_I = '1' then
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gpo0_reg <= (others => '0');
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gpo1_reg <= (others => '0');
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timer_en <= (others => '0');
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timer_inten <= (others => '0');
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elsif (STB_I and CYC_I and WE_I) = '1' then
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reg_data_wr <= DAT_I;
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case ADDR_I(6 downto 2) is
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when "00000" =>
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if SEL_I(0) = '1' then
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gpo0_reg(7 downto 0) <= DAT_I(7 downto 0);
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end if;
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if SEL_I(1) = '1' then
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gpo0_reg(15 downto 8) <= DAT_I(15 downto 8);
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end if;
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if SEL_I(2) = '1' then
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gpo0_reg(23 downto 16) <= DAT_I(23 downto 16);
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end if;
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if SEL_I(3) = '1' then
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gpo0_reg(31 downto 24) <= DAT_I(31 downto 24);
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end if;
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when "00001" =>
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if SEL_I(0) = '1' then
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gpo1_reg(7 downto 0) <= DAT_I(7 downto 0);
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end if;
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if SEL_I(1) = '1' then
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gpo1_reg(15 downto 8) <= DAT_I(15 downto 8);
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end if;
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if SEL_I(2) = '1' then
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gpo1_reg(23 downto 16) <= DAT_I(23 downto 16);
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end if;
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if SEL_I(3) = '1' then
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gpo1_reg(31 downto 24) <= DAT_I(31 downto 24);
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end if;
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when "00010" =>
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cnt_usec_we <= '1';
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when "00011" =>
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cnt_sec_we <= '1';
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when "00110" => -- timer control
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for i in 0 to num_timers-1 loop
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timer_en(i) <= DAT_I(2*i+0);
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timer_inten(i) <= DAT_I(2*i+1);
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end loop;
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when "00111" => -- timer status
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for i in 0 to num_timers-1 loop
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timer_irq_ack(i) <= DAT_I(2*i); -- IRQ acknowledge
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end loop;
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when "01000" => -- timer count 0
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timer_cnt_we(0) <= '1';
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when "01001" => -- timer count 1
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timer_cnt_we(1) <= '1';
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when "01100" => -- timer compare 0
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timer_cmp_we(0) <= '1';
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when "01101" => -- timer compare 1
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timer_cmp_we(1) <= '1';
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when others => null;
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end case;
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end if;
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end if;
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end process;
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registers_read:
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process(CLK_I)
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begin
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if rising_edge(CLK_I) then
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ACK_O <= '0';
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if (STB_I and CYC_I) = '1' then
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ACK_O <= not WE_I;
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DAT_O <= (others => '0');
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case ADDR_I(6 downto 2) is
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when "00000" =>
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DAT_O <= gpi0_reg;
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when "00001" =>
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DAT_O <= gpi1_reg;
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when "00010" =>
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DAT_O <= cnt_usec;
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when "00011" =>
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DAT_O <= cnt_sec;
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when "00110" => -- timer control
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for i in 0 to num_timers-1 loop
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DAT_O(2*i+0) <= timer_en(i);
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DAT_O(2*i+1) <= timer_inten(i);
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end loop;
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when "00111" => -- timer status
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for i in 0 to num_timers-1 loop
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DAT_O(2*i+0) <= timer_irq(i);
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DAT_O(2*i+1) <= timer_ovl(i);
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end loop;
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when "01000" => -- timer count 0
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DAT_O <= timer_cnt(0);
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when "01001" => -- timer count 1
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DAT_O <= timer_cnt(1);
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when "01100" => -- timer compare 0
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DAT_O <= timer_cmp(0);
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when "01101" => -- timer compare 1
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DAT_O <= timer_cmp(1);
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when others => null;
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end case;
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end if;
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end if;
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end process;
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cnt_usec_tick:
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process(CLK_I)
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begin
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if rising_edge(CLK_I) then
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cnt_usec_en <= '0';
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if tick_usec >= tick_usec_t'high then
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tick_usec <= 0;
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cnt_usec_en <= '1';
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else
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tick_usec <= tick_usec + 1;
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end if;
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end if;
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end process;
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-- H/W Clock
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cnt_usec_clock:
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process(CLK_I)
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begin
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if rising_edge(CLK_I) then
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cnt_sec_en <= '0';
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if cnt_usec_we = '1' then
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cnt_usec <= reg_data_wr;
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elsif cnt_usec_en = '1' then
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if cnt_usec >= to_unsigned(1E6 - 1, 32) then
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cnt_usec <= (others => '0');
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cnt_sec_en <= '1';
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else
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cnt_usec <= cnt_usec + 1;
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end if;
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end if;
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end if;
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end process;
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cnt_sec_clock:
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process(CLK_I)
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begin
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if rising_edge(CLK_I) then
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if cnt_sec_we = '1' then
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cnt_sec <= reg_data_wr;
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elsif cnt_sec_en = '1' then
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cnt_sec <= cnt_sec + 1;
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end if;
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end if;
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end process;
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-- Interrupt timer
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proc_int_timer:
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process(CLK_I)
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begin
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if rising_edge(CLK_I) then
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for i in 0 to num_timers-1 loop
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if RST_I = '1' then
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timer_ovl(i) <= '0';
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timer_irq(i) <= '0';
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elsif timer_irq_ack(i) = '1' then
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timer_ovl(i) <= '0';
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timer_irq(i) <= '0';
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elsif timer_cnt_we(i) = '1' then
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timer_cnt(i) <= reg_data_wr;
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elsif timer_en(i) = '1' then
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if timer_cnt(i) >= timer_cmp(i) then
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timer_cnt(i) <= (others => '0');
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if timer_inten(i) = '1' then
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if timer_irq(i) = '1' then
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timer_ovl(i) <= '1';
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end if;
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timer_irq(i) <= '1';
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end if;
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else
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timer_cnt(i) <= timer_cnt(i) + 1;
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end if;
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end if;
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end loop;
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end if;
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end process;
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proc_int_timer_reload:
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process(CLK_I)
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begin
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if rising_edge(CLK_I) then
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for i in 0 to num_timers-1 loop
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if timer_cmp_we(i) = '1' then
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timer_cmp(i) <= reg_data_wr;
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end if;
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end loop;
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end if;
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end process;
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------------------------------------------------------------------
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end behavior;
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