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git-svn-id: http://moon:8086/svn/vhdl/trunk@731 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2010-02-07 20:46:27 +00:00
parent 823dd066c2
commit 06c9683eea
4 changed files with 54 additions and 54 deletions
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projects/mips_sys/ise101/mips_sys/mips_sys.syr
+30 -30
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@@ -4,13 +4,13 @@ Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.08 secs
Total CPU time to Xst completion: 0.06 secs
--> Parameter xsthdpdir set to W:/vhdl/projects/mips_sys/ise101/mips_sys/xst
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.08 secs
Total CPU time to Xst completion: 0.06 secs
--> Reading design: mips_sys.prj
@@ -189,8 +189,7 @@ Architecture behavioral of Entity async_port_wb is up to date.
Compiling vhdl file "W:/vhdl/lib/uart/uart_wb.vhd" in Library work.
Architecture behavior of Entity uart_wb is up to date.
Compiling vhdl file "W:/vhdl/projects/mips_sys/src/clockgen_virtex4.vhd" in Library work.
Entity <clockgen> compiled.
Entity <clockgen> (Architecture <tech>) compiled.
Architecture tech of Entity clockgen is up to date.
Compiling vhdl file "W:/vhdl/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd" in Library work.
Architecture struct of Entity sdram_ctrl_frontend64_wb is up to date.
Compiling vhdl file "W:/vhdl/lib/VGA_ctrl/src/vga_frontend64.vhd" in Library work.
@@ -202,7 +201,8 @@ Architecture behavior of Entity ps2_wb is up to date.
Compiling vhdl file "W:/vhdl/lib/ps2_port/src/ps2_phy_virtex.vhd" in Library work.
Architecture behavioral of Entity ps2_phy is up to date.
Compiling vhdl file "W:/vhdl/projects/mips_sys/src/mips_sys.vhd" in Library work.
Architecture behavior of Entity mips_sys is up to date.
Entity <mips_sys> compiled.
Entity <mips_sys> (Architecture <behavior>) compiled.
=========================================================================
* Design Hierarchy Analysis *
@@ -4865,28 +4865,28 @@ inst_rom_wb/inst_rom/bs_update0 | BUFG
Asynchronous Control Signals Information:
----------------------------------------
-----------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------+-------+
Control Signal | Buffer(FF name) | Load |
-----------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------+-------+
RST_O_4(inst_clockgen/sys_rst_out_10:Q) | NONE(inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/inst_gray_counter_w/bcnt_3)| 289 |
inst_rom_wb/inst_rom/bs_rst(inst_rom_wb/inst_rom/BSCAN_VIRTEX4_inst1:RESET) | NONE(inst_rom_wb/inst_rom/user_rego_15) | 96 |
RST_O(inst_clockgen/sys_rst_out:Q) | NONE(inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/inst_gray_counter_w/gcnt_2) | 75 |
inst_ac97_wb/inst_ac_io/ac_reset(inst_ac97_wb/inst_ac_io/ac_reset:Q) | NONE(inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_19_BRB0) | 52 |
inst_ac97_wb/tx_fifo_rst(inst_ac97_wb/tx_fifo_rst1:O) | NONE(inst_ac97_wb/inst_tx_fifo/inst_fifo_sync_ctrl/pR_0) | 29 |
inst_vga_frontend/blit_reset(inst_vga_frontend/blit_reset1:O) | NONE(inst_vga_frontend/inst_blitfifo/inst_fifo_sync_ctrl/pR_4) | 21 |
inst_clockgen/sdr0_lock_inv(inst_clockgen/sdr0_lock_inv1_INV_0:O) | NONE(inst_clockgen/reset_pipe2_192) | 20 |
inst_clockgen/vga_fx_lock_inv(inst_clockgen/vga_fx_lock_inv1_INV_0:O) | NONE(inst_clockgen/vga_fx_lock_inv_shift12) | 20 |
rst_in(rst_in1:O) | NONE(inst_clockgen/reset_pipe0_192) | 20 |
inst_clockgen/sys_rst_out_or0000(inst_clockgen/sys_rst_out_or0000:O) | NONE(inst_clockgen/sys_rst_out_3) | 17 |
inst_ps2_phy_0/Inst_debounce_clk/output_and0000(inst_ps2_phy_0/Inst_debounce_clk/output_and00001:O) | NONE(inst_ps2_phy_0/Inst_debounce_clk/input_last) | 1 |
inst_ps2_phy_0/Inst_debounce_clk/output_and0001(inst_ps2_phy_0/Inst_debounce_clk/output_and00011:O) | NONE(inst_ps2_phy_0/Inst_debounce_clk/input_last) | 1 |
inst_ps2_phy_0/Inst_debounce_data/output_and0000(inst_ps2_phy_0/Inst_debounce_data/output_and00001:O)| NONE(inst_ps2_phy_0/Inst_debounce_data/input_last) | 1 |
inst_ps2_phy_0/Inst_debounce_data/output_and0001(inst_ps2_phy_0/Inst_debounce_data/output_and00011:O)| NONE(inst_ps2_phy_0/Inst_debounce_data/input_last) | 1 |
inst_ps2_phy_1/Inst_debounce_clk/output_and0000(inst_ps2_phy_1/Inst_debounce_clk/output_and00001:O) | NONE(inst_ps2_phy_1/Inst_debounce_clk/input_last) | 1 |
inst_ps2_phy_1/Inst_debounce_clk/output_and0001(inst_ps2_phy_1/Inst_debounce_clk/output_and00011:O) | NONE(inst_ps2_phy_1/Inst_debounce_clk/input_last) | 1 |
inst_ps2_phy_1/Inst_debounce_data/output_and0000(inst_ps2_phy_1/Inst_debounce_data/output_and00001:O)| NONE(inst_ps2_phy_1/Inst_debounce_data/input_last) | 1 |
inst_ps2_phy_1/Inst_debounce_data/output_and0001(inst_ps2_phy_1/Inst_debounce_data/output_and00011:O)| NONE(inst_ps2_phy_1/Inst_debounce_data/input_last) | 1 |
-----------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------+-------+
-----------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------+-------+
Control Signal | Buffer(FF name) | Load |
-----------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------+-------+
RST_O_4(inst_clockgen/sys_rst_out_10:Q) | NONE(inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd2)| 289 |
inst_rom_wb/inst_rom/bs_rst(inst_rom_wb/inst_rom/BSCAN_VIRTEX4_inst1:RESET) | NONE(inst_rom_wb/inst_rom/user_regi_422) | 96 |
RST_O(inst_clockgen/sys_rst_out:Q) | NONE(inst_sdram_ctrl_frontend_wb/inst_cat_fifo/inst_fifo_sync_ctrl/pR_1) | 75 |
inst_ac97_wb/inst_ac_io/ac_reset(inst_ac97_wb/inst_ac_io/ac_reset:Q) | NONE(inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_18) | 52 |
inst_ac97_wb/tx_fifo_rst(inst_ac97_wb/tx_fifo_rst1:O) | NONE(inst_ac97_wb/inst_tx_fifo/inst_fifo_sync_ctrl/diff_6) | 29 |
inst_vga_frontend/blit_reset(inst_vga_frontend/blit_reset1:O) | NONE(inst_vga_frontend/inst_blitfifo/inst_fifo_sync_ctrl/pR_0) | 21 |
inst_clockgen/sdr0_lock_inv(inst_clockgen/sdr0_lock_inv1_INV_0:O) | NONE(inst_clockgen/sdr0_lock_inv_shift19) | 20 |
inst_clockgen/vga_fx_lock_inv(inst_clockgen/vga_fx_lock_inv1_INV_0:O) | NONE(inst_clockgen/vga_fx_lock_inv_shift13) | 20 |
rst_in(rst_in1:O) | NONE(rst_in_shift12) | 20 |
inst_clockgen/sys_rst_out_or0000(inst_clockgen/sys_rst_out_or0000:O) | NONE(inst_clockgen/sys_rst_out_4) | 17 |
inst_ps2_phy_0/Inst_debounce_clk/output_and0000(inst_ps2_phy_0/Inst_debounce_clk/output_and00001:O) | NONE(inst_ps2_phy_0/Inst_debounce_clk/input_last) | 1 |
inst_ps2_phy_0/Inst_debounce_clk/output_and0001(inst_ps2_phy_0/Inst_debounce_clk/output_and00011:O) | NONE(inst_ps2_phy_0/Inst_debounce_clk/input_last) | 1 |
inst_ps2_phy_0/Inst_debounce_data/output_and0000(inst_ps2_phy_0/Inst_debounce_data/output_and00001:O)| NONE(inst_ps2_phy_0/Inst_debounce_data/input_last) | 1 |
inst_ps2_phy_0/Inst_debounce_data/output_and0001(inst_ps2_phy_0/Inst_debounce_data/output_and00011:O)| NONE(inst_ps2_phy_0/Inst_debounce_data/input_last) | 1 |
inst_ps2_phy_1/Inst_debounce_clk/output_and0000(inst_ps2_phy_1/Inst_debounce_clk/output_and00001:O) | NONE(inst_ps2_phy_1/Inst_debounce_clk/input_last) | 1 |
inst_ps2_phy_1/Inst_debounce_clk/output_and0001(inst_ps2_phy_1/Inst_debounce_clk/output_and00011:O) | NONE(inst_ps2_phy_1/Inst_debounce_clk/input_last) | 1 |
inst_ps2_phy_1/Inst_debounce_data/output_and0000(inst_ps2_phy_1/Inst_debounce_data/output_and00001:O)| NONE(inst_ps2_phy_1/Inst_debounce_data/input_last) | 1 |
inst_ps2_phy_1/Inst_debounce_data/output_and0001(inst_ps2_phy_1/Inst_debounce_data/output_and00011:O)| NONE(inst_ps2_phy_1/Inst_debounce_data/input_last) | 1 |
-----------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------+-------+
Timing Summary:
---------------
@@ -5184,12 +5184,12 @@ Delay: 9.843ns (Levels of Logic = 11)
=========================================================================
Total REAL time to Xst completion: 122.00 secs
Total CPU time to Xst completion: 122.11 secs
Total REAL time to Xst completion: 118.00 secs
Total CPU time to Xst completion: 117.75 secs
-->
Total memory usage is 337652 kilobytes
Total memory usage is 338676 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 993 ( 0 filtered)