diff --git a/projects/mips_sys/ise101/mips_sys/mips_sys.par b/projects/mips_sys/ise101/mips_sys/mips_sys.par index a46559a..0037ff0 100644 --- a/projects/mips_sys/ise101/mips_sys/mips_sys.par +++ b/projects/mips_sys/ise101/mips_sys/mips_sys.par @@ -1,7 +1,7 @@ Release 10.1.03 par K.39 (nt) Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. -JUPITER:: Sun Feb 07 20:01:09 2010 +JUPITER:: Sun Feb 07 20:58:29 2010 par -w -intstyle ise -ol high -xe n -t 1 mips_sys_map.ncd mips_sys.ncd mips_sys.pcf @@ -44,46 +44,46 @@ Finished initial Timing Analysis. REAL time: 14 secs Starting Router -Phase 1: 47772 unrouted; REAL time: 16 secs +Phase 1: 47772 unrouted; REAL time: 15 secs Phase 2: 40729 unrouted; REAL time: 16 secs -Phase 3: 15700 unrouted; REAL time: 23 secs +Phase 3: 15700 unrouted; REAL time: 22 secs Phase 4: 15700 unrouted; (296275) REAL time: 23 secs -Phase 5: 16428 unrouted; (12142) REAL time: 30 secs +Phase 5: 16428 unrouted; (12142) REAL time: 29 secs -Phase 6: 16484 unrouted; (815) REAL time: 30 secs +Phase 6: 16484 unrouted; (815) REAL time: 29 secs -Phase 7: 0 unrouted; (10463) REAL time: 1 mins 3 secs +Phase 7: 0 unrouted; (10463) REAL time: 1 mins Updating file: mips_sys.ncd with current fully routed design. -Phase 8: 0 unrouted; (10463) REAL time: 2 mins 52 secs +Phase 8: 0 unrouted; (10463) REAL time: 2 mins 43 secs -Phase 9: 0 unrouted; (6271) REAL time: 3 mins 5 secs +Phase 9: 0 unrouted; (6271) REAL time: 2 mins 55 secs -Phase 10: 0 unrouted; (6221) REAL time: 3 mins 12 secs +Phase 10: 0 unrouted; (6221) REAL time: 3 mins 2 secs -Phase 11: 0 unrouted; (6221) REAL time: 3 mins 12 secs +Phase 11: 0 unrouted; (6221) REAL time: 3 mins 3 secs Updating file: mips_sys.ncd with current fully routed design. -Phase 12: 0 unrouted; (5742) REAL time: 4 mins 33 secs +Phase 12: 0 unrouted; (5742) REAL time: 4 mins 18 secs -Phase 13: 0 unrouted; (5742) REAL time: 4 mins 48 secs +Phase 13: 0 unrouted; (5742) REAL time: 4 mins 32 secs Updating file: mips_sys.ncd with current fully routed design. -Phase 14: 0 unrouted; (483) REAL time: 5 mins 13 secs +Phase 14: 0 unrouted; (483) REAL time: 4 mins 57 secs -Phase 15: 0 unrouted; (483) REAL time: 5 mins 18 secs +Phase 15: 0 unrouted; (483) REAL time: 5 mins 1 secs -Phase 16: 0 unrouted; (483) REAL time: 5 mins 23 secs +Phase 16: 0 unrouted; (483) REAL time: 5 mins 6 secs -Total REAL time to Router completion: 5 mins 26 secs -Total CPU time to Router completion: 5 mins 11 secs +Total REAL time to Router completion: 5 mins 8 secs +Total CPU time to Router completion: 4 mins 55 secs Partition Implementation Status ------------------------------- @@ -189,8 +189,8 @@ Generating Pad Report. All signals are completely routed. -Total REAL time to PAR completion: 5 mins 35 secs -Total CPU time to PAR completion: 5 mins 17 secs +Total REAL time to PAR completion: 5 mins 17 secs +Total CPU time to PAR completion: 5 mins 1 secs Peak Memory Usage: 418 MB diff --git a/projects/mips_sys/ise101/mips_sys/mips_sys.syr b/projects/mips_sys/ise101/mips_sys/mips_sys.syr index e0a0056..3763f79 100644 --- a/projects/mips_sys/ise101/mips_sys/mips_sys.syr +++ b/projects/mips_sys/ise101/mips_sys/mips_sys.syr @@ -4,13 +4,13 @@ Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. Total REAL time to Xst completion: 0.00 secs -Total CPU time to Xst completion: 0.08 secs +Total CPU time to Xst completion: 0.06 secs --> Parameter xsthdpdir set to W:/vhdl/projects/mips_sys/ise101/mips_sys/xst Total REAL time to Xst completion: 0.00 secs -Total CPU time to Xst completion: 0.08 secs +Total CPU time to Xst completion: 0.06 secs --> Reading design: mips_sys.prj @@ -189,8 +189,7 @@ Architecture behavioral of Entity async_port_wb is up to date. Compiling vhdl file "W:/vhdl/lib/uart/uart_wb.vhd" in Library work. Architecture behavior of Entity uart_wb is up to date. Compiling vhdl file "W:/vhdl/projects/mips_sys/src/clockgen_virtex4.vhd" in Library work. -Entity compiled. -Entity (Architecture ) compiled. +Architecture tech of Entity clockgen is up to date. Compiling vhdl file "W:/vhdl/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd" in Library work. Architecture struct of Entity sdram_ctrl_frontend64_wb is up to date. Compiling vhdl file "W:/vhdl/lib/VGA_ctrl/src/vga_frontend64.vhd" in Library work. @@ -202,7 +201,8 @@ Architecture behavior of Entity ps2_wb is up to date. Compiling vhdl file "W:/vhdl/lib/ps2_port/src/ps2_phy_virtex.vhd" in Library work. Architecture behavioral of Entity ps2_phy is up to date. Compiling vhdl file "W:/vhdl/projects/mips_sys/src/mips_sys.vhd" in Library work. -Architecture behavior of Entity mips_sys is up to date. +Entity compiled. +Entity (Architecture ) compiled. ========================================================================= * Design Hierarchy Analysis * @@ -4865,28 +4865,28 @@ inst_rom_wb/inst_rom/bs_update0 | BUFG Asynchronous Control Signals Information: ---------------------------------------- ------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------+-------+ -Control Signal | Buffer(FF name) | Load | ------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------+-------+ -RST_O_4(inst_clockgen/sys_rst_out_10:Q) | NONE(inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/inst_gray_counter_w/bcnt_3)| 289 | -inst_rom_wb/inst_rom/bs_rst(inst_rom_wb/inst_rom/BSCAN_VIRTEX4_inst1:RESET) | NONE(inst_rom_wb/inst_rom/user_rego_15) | 96 | -RST_O(inst_clockgen/sys_rst_out:Q) | NONE(inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/inst_gray_counter_w/gcnt_2) | 75 | -inst_ac97_wb/inst_ac_io/ac_reset(inst_ac97_wb/inst_ac_io/ac_reset:Q) | NONE(inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_19_BRB0) | 52 | -inst_ac97_wb/tx_fifo_rst(inst_ac97_wb/tx_fifo_rst1:O) | NONE(inst_ac97_wb/inst_tx_fifo/inst_fifo_sync_ctrl/pR_0) | 29 | -inst_vga_frontend/blit_reset(inst_vga_frontend/blit_reset1:O) | NONE(inst_vga_frontend/inst_blitfifo/inst_fifo_sync_ctrl/pR_4) | 21 | -inst_clockgen/sdr0_lock_inv(inst_clockgen/sdr0_lock_inv1_INV_0:O) | NONE(inst_clockgen/reset_pipe2_192) | 20 | -inst_clockgen/vga_fx_lock_inv(inst_clockgen/vga_fx_lock_inv1_INV_0:O) | NONE(inst_clockgen/vga_fx_lock_inv_shift12) | 20 | -rst_in(rst_in1:O) | NONE(inst_clockgen/reset_pipe0_192) | 20 | -inst_clockgen/sys_rst_out_or0000(inst_clockgen/sys_rst_out_or0000:O) | NONE(inst_clockgen/sys_rst_out_3) | 17 | -inst_ps2_phy_0/Inst_debounce_clk/output_and0000(inst_ps2_phy_0/Inst_debounce_clk/output_and00001:O) | NONE(inst_ps2_phy_0/Inst_debounce_clk/input_last) | 1 | -inst_ps2_phy_0/Inst_debounce_clk/output_and0001(inst_ps2_phy_0/Inst_debounce_clk/output_and00011:O) | NONE(inst_ps2_phy_0/Inst_debounce_clk/input_last) | 1 | -inst_ps2_phy_0/Inst_debounce_data/output_and0000(inst_ps2_phy_0/Inst_debounce_data/output_and00001:O)| NONE(inst_ps2_phy_0/Inst_debounce_data/input_last) | 1 | -inst_ps2_phy_0/Inst_debounce_data/output_and0001(inst_ps2_phy_0/Inst_debounce_data/output_and00011:O)| NONE(inst_ps2_phy_0/Inst_debounce_data/input_last) | 1 | -inst_ps2_phy_1/Inst_debounce_clk/output_and0000(inst_ps2_phy_1/Inst_debounce_clk/output_and00001:O) | NONE(inst_ps2_phy_1/Inst_debounce_clk/input_last) | 1 | -inst_ps2_phy_1/Inst_debounce_clk/output_and0001(inst_ps2_phy_1/Inst_debounce_clk/output_and00011:O) | NONE(inst_ps2_phy_1/Inst_debounce_clk/input_last) | 1 | -inst_ps2_phy_1/Inst_debounce_data/output_and0000(inst_ps2_phy_1/Inst_debounce_data/output_and00001:O)| NONE(inst_ps2_phy_1/Inst_debounce_data/input_last) | 1 | -inst_ps2_phy_1/Inst_debounce_data/output_and0001(inst_ps2_phy_1/Inst_debounce_data/output_and00011:O)| NONE(inst_ps2_phy_1/Inst_debounce_data/input_last) | 1 | ------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------+-------+ +-----------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------+-------+ +Control Signal | Buffer(FF name) | Load | +-----------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------+-------+ +RST_O_4(inst_clockgen/sys_rst_out_10:Q) | NONE(inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd2)| 289 | +inst_rom_wb/inst_rom/bs_rst(inst_rom_wb/inst_rom/BSCAN_VIRTEX4_inst1:RESET) | NONE(inst_rom_wb/inst_rom/user_regi_422) | 96 | +RST_O(inst_clockgen/sys_rst_out:Q) | NONE(inst_sdram_ctrl_frontend_wb/inst_cat_fifo/inst_fifo_sync_ctrl/pR_1) | 75 | +inst_ac97_wb/inst_ac_io/ac_reset(inst_ac97_wb/inst_ac_io/ac_reset:Q) | NONE(inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_18) | 52 | +inst_ac97_wb/tx_fifo_rst(inst_ac97_wb/tx_fifo_rst1:O) | NONE(inst_ac97_wb/inst_tx_fifo/inst_fifo_sync_ctrl/diff_6) | 29 | +inst_vga_frontend/blit_reset(inst_vga_frontend/blit_reset1:O) | NONE(inst_vga_frontend/inst_blitfifo/inst_fifo_sync_ctrl/pR_0) | 21 | +inst_clockgen/sdr0_lock_inv(inst_clockgen/sdr0_lock_inv1_INV_0:O) | NONE(inst_clockgen/sdr0_lock_inv_shift19) | 20 | +inst_clockgen/vga_fx_lock_inv(inst_clockgen/vga_fx_lock_inv1_INV_0:O) | NONE(inst_clockgen/vga_fx_lock_inv_shift13) | 20 | +rst_in(rst_in1:O) | NONE(rst_in_shift12) | 20 | +inst_clockgen/sys_rst_out_or0000(inst_clockgen/sys_rst_out_or0000:O) | NONE(inst_clockgen/sys_rst_out_4) | 17 | +inst_ps2_phy_0/Inst_debounce_clk/output_and0000(inst_ps2_phy_0/Inst_debounce_clk/output_and00001:O) | NONE(inst_ps2_phy_0/Inst_debounce_clk/input_last) | 1 | +inst_ps2_phy_0/Inst_debounce_clk/output_and0001(inst_ps2_phy_0/Inst_debounce_clk/output_and00011:O) | NONE(inst_ps2_phy_0/Inst_debounce_clk/input_last) | 1 | +inst_ps2_phy_0/Inst_debounce_data/output_and0000(inst_ps2_phy_0/Inst_debounce_data/output_and00001:O)| NONE(inst_ps2_phy_0/Inst_debounce_data/input_last) | 1 | +inst_ps2_phy_0/Inst_debounce_data/output_and0001(inst_ps2_phy_0/Inst_debounce_data/output_and00011:O)| NONE(inst_ps2_phy_0/Inst_debounce_data/input_last) | 1 | +inst_ps2_phy_1/Inst_debounce_clk/output_and0000(inst_ps2_phy_1/Inst_debounce_clk/output_and00001:O) | NONE(inst_ps2_phy_1/Inst_debounce_clk/input_last) | 1 | +inst_ps2_phy_1/Inst_debounce_clk/output_and0001(inst_ps2_phy_1/Inst_debounce_clk/output_and00011:O) | NONE(inst_ps2_phy_1/Inst_debounce_clk/input_last) | 1 | +inst_ps2_phy_1/Inst_debounce_data/output_and0000(inst_ps2_phy_1/Inst_debounce_data/output_and00001:O)| NONE(inst_ps2_phy_1/Inst_debounce_data/input_last) | 1 | +inst_ps2_phy_1/Inst_debounce_data/output_and0001(inst_ps2_phy_1/Inst_debounce_data/output_and00011:O)| NONE(inst_ps2_phy_1/Inst_debounce_data/input_last) | 1 | +-----------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------+-------+ Timing Summary: --------------- @@ -5184,12 +5184,12 @@ Delay: 9.843ns (Levels of Logic = 11) ========================================================================= -Total REAL time to Xst completion: 122.00 secs -Total CPU time to Xst completion: 122.11 secs +Total REAL time to Xst completion: 118.00 secs +Total CPU time to Xst completion: 117.75 secs --> -Total memory usage is 337652 kilobytes +Total memory usage is 338676 kilobytes Number of errors : 0 ( 0 filtered) Number of warnings : 993 ( 0 filtered) diff --git a/projects/mips_sys/ise101/mips_sys/mips_sys.twr b/projects/mips_sys/ise101/mips_sys/mips_sys.twr index 800df48..5b2af52 100644 --- a/projects/mips_sys/ise101/mips_sys/mips_sys.twr +++ b/projects/mips_sys/ise101/mips_sys/mips_sys.twr @@ -1430,7 +1430,7 @@ Design statistics: ------------------------------------Footnotes----------------------------------- 1) The minimum period statistic assumes all single cycle delays. -Analysis completed Sun Feb 07 20:07:12 2010 +Analysis completed Sun Feb 07 21:04:11 2010 -------------------------------------------------------------------------------- Trace Settings: diff --git a/projects/mips_sys/ise101/mips_sys/mips_sys_map.mrp b/projects/mips_sys/ise101/mips_sys/mips_sys_map.mrp index a1da64d..70035dd 100644 --- a/projects/mips_sys/ise101/mips_sys/mips_sys_map.mrp +++ b/projects/mips_sys/ise101/mips_sys/mips_sys_map.mrp @@ -10,8 +10,8 @@ Target Device : xc4vsx35 Target Package : ff668 Target Speed : -10 Stepping Level : ES -Mapper Version : virtex4 -- $Revision: 1.1 $ -Mapped Date : Sun Feb 07 19:52:23 2010 +Mapper Version : virtex4 -- $Revision: 1.2 $ +Mapped Date : Sun Feb 07 20:50:10 2010 Design Summary -------------- @@ -43,8 +43,8 @@ Logic Distribution: Number of BSCAN_VIRTEX4s: 1 out of 4 25% Peak Memory Usage: 510 MB -Total REAL time to MAP completion: 8 mins 29 secs -Total CPU time to MAP completion: 8 mins 20 secs +Total REAL time to MAP completion: 8 mins 4 secs +Total CPU time to MAP completion: 7 mins 57 secs Table of Contents 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