- self checking TB with incremented data

git-svn-id: http://moon:8086/svn/vhdl/trunk@1344 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
2016-12-18 10:33:51 +00:00
parent 262d045890
commit 0300be76ce
3 changed files with 21 additions and 22 deletions
+1 -1
View File
@@ -12,4 +12,4 @@ do {tb_juart_tx_rx.wdo}
view wave
view structure
view signals
run 10.0us
run 880.0us
+3 -3
View File
@@ -11,9 +11,9 @@ add wave -noupdate -format Logic /tb_juart_tx_rx/serial_in
add wave -noupdate -format Logic /tb_juart_tx_rx/data_strobe
add wave -noupdate -format Literal -radix hexadecimal /tb_juart_tx_rx/data_out
add wave -noupdate -format Literal -radix hexadecimal /tb_juart_tx_rx/data_rx
add wave -noupdate -format Literal -radix hexadecimal /tb_juart_tx_rx/data_tx
add wave -noupdate -format Literal /tb_juart_tx_rx/data_tx
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {8475278 ps} 0}
WaveRestoreCursors {{Cursor 1} {0 ps} 0}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
@@ -27,4 +27,4 @@ configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
update
WaveRestoreZoom {0 ps} {10500 ns}
WaveRestoreZoom {0 ps} {924 us}
+17 -18
View File
@@ -53,7 +53,7 @@ architecture behave of tb_juart_tx_rx is
signal baud_count : unsigned(15 downto 0);
signal baudrate : unsigned(15 downto 0) := X"0001";
signal data_rx : unsigned(7 downto 0);
signal data_tx : unsigned(7 downto 0) := X"AA";
signal data_tx : unsigned(7 downto 0);
begin
@@ -88,10 +88,17 @@ CLK_GEN: process
clk <= not clk;
end process;
PROC_DATAREG: process
PROC_DATAREG_RX: process
begin
wait until rising_edge(clk) and data_strobe = '1';
data_rx <= data_out;
assert data_out = data_tx report "Data mismatch" severity failure;
end process;
PROC_DATAREG_TX: process
begin
wait until rising_edge(clk) and send_character = '1';
data_tx <= data_in;
end process;
baud_timer:
@@ -121,22 +128,14 @@ STIMULUS: process
rst <= '0';
wait for 3*CLK_PERIOD;
wait until rising_edge(clk);
data_in <= X"A5";
wait until rising_edge(clk) and Tx_complete = '1';
send_character <= '1';
wait until rising_edge(clk) and Tx_complete = '0';
send_character <= '0';
wait until rising_edge(clk) and Tx_complete = '1';
data_in <= X"AA";
wait until rising_edge(clk) and Tx_complete = '1';
send_character <= '1';
wait until rising_edge(clk) and Tx_complete = '0';
send_character <= '0';
data_in <= X"55";
wait until rising_edge(clk) and Tx_complete = '1';
send_character <= '1';
wait until rising_edge(clk) and Tx_complete = '0';
send_character <= '0';
for i in 0 to 255 loop
wait until rising_edge(clk) and Tx_complete = '1';
data_in <= to_unsigned(i, 8);
send_character <= '1';
wait until rising_edge(clk) and Tx_complete = '0';
send_character <= '0';
end loop;
wait;
end process;