diff --git a/lib/uart/sim/tb_juart_tx_rx.fdo b/lib/uart/sim/tb_juart_tx_rx.fdo
index ccbe4bf..aa5b96d 100644
--- a/lib/uart/sim/tb_juart_tx_rx.fdo
+++ b/lib/uart/sim/tb_juart_tx_rx.fdo
@@ -12,4 +12,4 @@ do {tb_juart_tx_rx.wdo}
 view wave
 view structure
 view signals
-run 10.0us
+run 880.0us
diff --git a/lib/uart/sim/tb_juart_tx_rx.wdo b/lib/uart/sim/tb_juart_tx_rx.wdo
index 1398efe..60b405c 100644
--- a/lib/uart/sim/tb_juart_tx_rx.wdo
+++ b/lib/uart/sim/tb_juart_tx_rx.wdo
@@ -11,9 +11,9 @@ add wave -noupdate -format Logic /tb_juart_tx_rx/serial_in
 add wave -noupdate -format Logic /tb_juart_tx_rx/data_strobe
 add wave -noupdate -format Literal -radix hexadecimal /tb_juart_tx_rx/data_out
 add wave -noupdate -format Literal -radix hexadecimal /tb_juart_tx_rx/data_rx
-add wave -noupdate -format Literal -radix hexadecimal /tb_juart_tx_rx/data_tx
+add wave -noupdate -format Literal /tb_juart_tx_rx/data_tx
 TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {8475278 ps} 0}
+WaveRestoreCursors {{Cursor 1} {0 ps} 0}
 configure wave -namecolwidth 150
 configure wave -valuecolwidth 100
 configure wave -justifyvalue left
@@ -27,4 +27,4 @@ configure wave -gridperiod 1
 configure wave -griddelta 40
 configure wave -timeline 0
 update
-WaveRestoreZoom {0 ps} {10500 ns}
+WaveRestoreZoom {0 ps} {924 us}
diff --git a/lib/uart/tb_juart_tx_rx.vhd b/lib/uart/tb_juart_tx_rx.vhd
index fd3df78..a7c3134 100644
--- a/lib/uart/tb_juart_tx_rx.vhd
+++ b/lib/uart/tb_juart_tx_rx.vhd
@@ -53,7 +53,7 @@ architecture behave of tb_juart_tx_rx is
 	signal baud_count		: unsigned(15 downto 0);
 	signal baudrate			: unsigned(15 downto 0) := X"0001";
 	signal data_rx			: unsigned(7 downto 0);
-	signal data_tx			: unsigned(7 downto 0) := X"AA";
+	signal data_tx			: unsigned(7 downto 0);
 	
 begin
 
@@ -88,10 +88,17 @@ CLK_GEN: process
 		clk <= not clk;
 	end process;
 
-PROC_DATAREG: process
+PROC_DATAREG_RX: process
 	begin
 		wait until rising_edge(clk) and data_strobe = '1';
 		data_rx <= data_out;
+		assert data_out = data_tx report "Data mismatch" severity failure;
+	end process;
+
+PROC_DATAREG_TX: process
+	begin
+		wait until rising_edge(clk) and send_character = '1';
+		data_tx <= data_in;
 	end process;
 
 baud_timer:
@@ -121,22 +128,14 @@ STIMULUS: process
 		rst <= '0';
 		wait for 3*CLK_PERIOD;
 		wait until rising_edge(clk);
-		data_in <= X"A5";
-		wait until rising_edge(clk) and Tx_complete = '1';
-		send_character <= '1';
-		wait until rising_edge(clk) and Tx_complete = '0';
-		send_character <= '0';
-		wait until rising_edge(clk) and Tx_complete = '1';
-		data_in <= X"AA";
-		wait until rising_edge(clk) and Tx_complete = '1';
-		send_character <= '1';
-		wait until rising_edge(clk) and Tx_complete = '0';
-		send_character <= '0';
-		data_in <= X"55";
-		wait until rising_edge(clk) and Tx_complete = '1';
-		send_character <= '1';
-		wait until rising_edge(clk) and Tx_complete = '0';
-		send_character <= '0';
+		
+		for i in 0 to 255 loop
+			wait until rising_edge(clk) and Tx_complete = '1';
+			data_in <= to_unsigned(i, 8);
+			send_character <= '1';
+			wait until rising_edge(clk) and Tx_complete = '0';
+			send_character <= '0';
+		end loop;
 		wait; 
 	
 	end process;