jens
010c1d2b65
git-svn-id: http://moon:8086/svn/vhdl/trunk@1426 cc03376c-175c-47c8-b038-4cd826a8556b
132 lines
2.6 KiB
VHDL
132 lines
2.6 KiB
VHDL
----------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 19:55:49 04/08/2007
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-- Design Name:
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-- Module Name: sipo - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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---- Uncomment the following library declaration if instantiating
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---- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity sipo is
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Generic ( width : integer := 8 );
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Port (
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rst : in STD_LOGIC;
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clk : in STD_LOGIC;
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srdyo : out STD_LOGIC;
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sdi : in STD_LOGIC;
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ssi : in STD_LOGIC;
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prdyi : in STD_LOGIC;
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pvo : out STD_LOGIC;
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pdo : out UNSIGNED (width-1 downto 0)
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);
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end sipo;
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architecture Behavioral of sipo is
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type sstate_t is (reset, idle, ready, sync, active);
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constant idle_pol : std_logic := '0';
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signal reg : UNSIGNED (width-1 downto 0);
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signal pvalid, shift_en, counter_srst, counter_rdy : std_logic;
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signal sstate, sstate_next : sstate_t;
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begin
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par_out:
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process (rst, clk, sdi, reg, shift_en, pvalid)
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begin
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if rst = '1' then
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reg <= (others => idle_pol);
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pvo <= '0';
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elsif rising_edge(clk) then
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if shift_en = '1' then
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reg <= reg(width-2 downto 0) & sdi;
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end if;
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pvo <= pvalid;
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end if;
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pdo <= reg;
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end process;
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counter:
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process (rst, clk, counter_srst)
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variable counter : integer range 0 to width-1;
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begin
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if rst = '1' then
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counter_rdy <= '0';
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elsif rising_edge(clk) then
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if counter_srst = '1' then
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counter := width-4;
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counter_rdy <= '0';
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elsif counter /= 0 then
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counter := counter - 1;
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else
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counter_rdy <= '1';
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end if;
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end if;
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end process;
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ser_sm:
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process (rst, clk, ssi, sstate, counter_rdy, prdyi)
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begin
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sstate_next <= sstate;
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shift_en <= '1';
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pvalid <= '0';
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counter_srst <= ssi;
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srdyo <= '0';
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case sstate is
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when reset =>
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sstate_next <= idle;
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when idle =>
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sstate_next <= ready;
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when ready =>
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srdyo <= prdyi;
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if ssi = '1' then
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sstate_next <= active;
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end if;
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when active =>
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if counter_rdy = '1' then
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sstate_next <= sync;
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end if;
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when sync =>
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pvalid <= '1';
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sstate_next <= idle;
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when others =>
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sstate_next <= idle;
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end case;
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end process;
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state_proc:
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process (rst, clk, sstate_next)
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begin
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if rst = '1' then
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sstate <= reset;
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elsif rising_edge(clk) then
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sstate <= sstate_next;
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end if;
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end process;
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end Behavioral;
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