124 lines
3.1 KiB
VHDL
124 lines
3.1 KiB
VHDL
-------------------------------------------------------------------------
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-- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
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-- This file: Testbench for JCPU
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-- also writes 'opc.lst' for JASM-assembler
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--
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-- Copyright (C) 2007 J. Ahrensfeld
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--
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-- This program is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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--
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-- For questions and ideas, please contact the author at jens@jayfield.org
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--
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--------------------------------------------------------------------------
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LIBRARY ieee;
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use IEEE.STD_LOGIC_1164.ALL;
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USE ieee.numeric_std.ALL;
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use std.textio.all; -- Imports the standard textio package.
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ENTITY tb_mips_embedded_syn IS
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END tb_mips_embedded_syn;
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ARCHITECTURE behavior OF tb_mips_embedded_syn IS
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COMPONENT mips_embedded_syn
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Port
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(
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sys_rst_n_in : in STD_LOGIC;
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sys_clk_in : in STD_LOGIC;
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sys_dip : in STD_LOGIC_VECTOR (7 downto 0);
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sys_btn : in STD_LOGIC_VECTOR (8 downto 0);
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sys_led : out STD_LOGIC_VECTOR (7 downto 0);
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sys_rx : in STD_LOGIC;
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sys_tx : out STD_LOGIC;
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sys_error : out STD_LOGIC_VECTOR (1 downto 0)
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);
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END COMPONENT;
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constant CLK_PERIOD : time := 10.0 ns;
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signal sys_rst_n_in : std_logic := '0';
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signal sys_clk_in : std_logic := '1';
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signal sys_led : STD_LOGIC_VECTOR (7 downto 0);
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signal sys_btn : STD_LOGIC_VECTOR (8 downto 0) := "000000000";
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signal sys_dip : STD_LOGIC_VECTOR (7 downto 0) := "10001001";
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signal sys_error : STD_LOGIC_VECTOR (1 downto 0);
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signal sys_rx : std_logic := '1';
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signal sys_tx : std_logic;
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BEGIN
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uut: mips_embedded_syn
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PORT MAP
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(
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sys_rst_n_in => sys_rst_n_in,
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sys_clk_in => sys_clk_in,
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sys_btn => sys_btn,
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sys_dip => sys_dip,
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sys_led => sys_led,
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sys_rx => sys_rx,
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sys_tx => sys_tx,
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sys_error => sys_error
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);
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CLK_GEN: process
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begin
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wait for CLK_PERIOD/2;
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sys_clk_in <= not sys_clk_in;
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end process;
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STIMULUS1: process
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begin
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wait for 3*CLK_PERIOD;
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wait until rising_edge(sys_clk_in);
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sys_rst_n_in <= '1';
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-- wait for 9994999*CLK_PERIOD;
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-- for i in 1 to 10000 loop
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-- wait for 100*CLK_PERIOD;
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-- sys_btn(3) <= '1';
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-- wait for 10*CLK_PERIOD;
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-- sys_btn(3) <= '0';
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-- end loop;
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wait until rising_edge(sys_clk_in) and now = 38980 ns;
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sys_btn <= "000001000";
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wait until rising_edge(sys_clk_in);
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sys_btn <= "000000000";
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wait;
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end process;
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STIMULUS2: process
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begin
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wait for 9999999*CLK_PERIOD;
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for i in 1 to 10000 loop
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wait for 137*CLK_PERIOD;
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sys_btn(4) <= '1';
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wait for 21*CLK_PERIOD;
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sys_btn(4) <= '0';
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end loop;
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wait;
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end process;
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END;
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