-------------------------------------------------------------------------
-- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
-- This file: Testbench for JCPU
--            also writes 'opc.lst' for JASM-assembler
--
-- Copyright (C) 2007 J. Ahrensfeld
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
--
-- For questions and ideas, please contact the author at jens@jayfield.org
--
--------------------------------------------------------------------------

LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;
use std.textio.all; --  Imports the standard textio package.

ENTITY tb_mips_embedded_syn IS
END tb_mips_embedded_syn;

ARCHITECTURE behavior OF tb_mips_embedded_syn IS 

	COMPONENT mips_embedded_syn
	Port 
	(
		sys_rst_n_in		: in  STD_LOGIC;
		sys_clk_in			: in  STD_LOGIC;
		sys_dip				: in  STD_LOGIC_VECTOR (7 downto 0);
		sys_btn				: in  STD_LOGIC_VECTOR (8 downto 0);
		sys_led				: out STD_LOGIC_VECTOR (7 downto 0);
		sys_rx				: in  STD_LOGIC;
		sys_tx				: out STD_LOGIC;
		sys_error			: out STD_LOGIC_VECTOR (1 downto 0)
	);
	END COMPONENT;

	constant CLK_PERIOD : time := 10.0 ns;

	signal sys_rst_n_in			: std_logic := '0';
	signal sys_clk_in			: std_logic := '1';
	signal sys_led	 			: STD_LOGIC_VECTOR (7 downto 0);
	signal sys_btn	 			: STD_LOGIC_VECTOR (8 downto 0) := "000000000";
	signal sys_dip	 			: STD_LOGIC_VECTOR (7 downto 0) := "10001001";
	signal sys_error 			: STD_LOGIC_VECTOR (1 downto 0);
	signal sys_rx				: std_logic := '1';
	signal sys_tx				: std_logic;
	
BEGIN

uut: mips_embedded_syn
	PORT MAP
	(
		sys_rst_n_in			=> sys_rst_n_in,
		sys_clk_in				=> sys_clk_in,
		sys_btn					=> sys_btn,
		sys_dip					=> sys_dip,
		sys_led					=> sys_led,
		sys_rx					=> sys_rx,
		sys_tx					=> sys_tx,
		sys_error				=> sys_error
	);

CLK_GEN: process
	begin
		wait for CLK_PERIOD/2;
		sys_clk_in <= not sys_clk_in;
	end process;

STIMULUS1: process
	begin

		wait for 3*CLK_PERIOD;
		wait until rising_edge(sys_clk_in);
		sys_rst_n_in <= '1';
	
		
		
--		wait for 9994999*CLK_PERIOD;
--		for i in 1 to 10000 loop
--			wait for 100*CLK_PERIOD;
--			sys_btn(3) <= '1';
--			wait for 10*CLK_PERIOD;
--			sys_btn(3) <= '0';
--		end loop;		
		
		wait until rising_edge(sys_clk_in) and now = 38980 ns;
		sys_btn <= "000001000";
		wait until rising_edge(sys_clk_in);
		sys_btn <= "000000000";

		wait; 
	
	end process;

STIMULUS2: process
	begin

	
		wait for 9999999*CLK_PERIOD;
		for i in 1 to 10000 loop
			wait for 137*CLK_PERIOD;
			sys_btn(4) <= '1';
			wait for 21*CLK_PERIOD;
			sys_btn(4) <= '0';
		end loop;		

		wait; 
	
	end process;

END;