jens
2440831a07
- cleaned up git-svn-id: http://moon:8086/svn/vhdl/trunk@1355 cc03376c-175c-47c8-b038-4cd826a8556b
137 lines
3.2 KiB
VHDL
137 lines
3.2 KiB
VHDL
-------------------------------------------------------------------------
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-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
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-- This file: cpu_embedded using cpu_core and rom
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--
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-- Copyright (C) 2007 J. Ahrensfeld
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--
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-- This program is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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--
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-- For questions and ideas, please contact the author at jens@jayfield.org
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--
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--------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.numeric_std.ALL;
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LIBRARY WORK;
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USE WORK.uart_types.all;
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entity tb_uart is
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end;
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architecture behave of tb_uart is
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-- Number of user data words for simulation
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constant CLK_PERIOD : time := 10 ns;
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constant BAUD_DIV : natural := 2;
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-- Common
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signal rst : std_logic := '1';
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signal clk : std_logic := '1';
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signal ctrl : ctrl_t;
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signal status : status_t;
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-- TX
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signal tx_we : std_logic := '0';
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signal tx_ser : std_logic;
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signal tx_din : unsigned(7 downto 0) := (others => '0');
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-- RX
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signal rx_re : std_logic := '0';
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signal rx_ser : std_logic := '1';
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signal rx_dout : unsigned(7 downto 0);
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-- Others
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signal data_rx : unsigned(7 downto 0);
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signal data_tx : unsigned(7 downto 0);
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signal count_rx : natural;
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begin
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rx_ser <= tx_ser;
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ctrl.baudrate <= to_unsigned(BAUD_DIV-1, ctrl.baudrate'length);
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dut : entity work.uart
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PORT MAP
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(
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rst => rst,
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clk => clk,
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we => tx_we,
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re => rx_re,
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din => tx_din,
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dout => rx_dout,
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ser_tx => tx_ser,
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ser_rx => rx_ser,
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ctrl => ctrl,
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status => status
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);
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CLK_GEN: process
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begin
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wait for CLK_PERIOD/2;
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clk <= not clk;
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end process;
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PROC_DATAREG_RX:
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process (clk)
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begin
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if rising_edge(clk) then
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if rst = '1' then
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count_rx <= 0;
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elsif status.rx_present = '1' and rx_re = '1' then
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-- assert rx_dout = count_rx report "Data mismatch" severity failure;
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data_rx <= rx_dout;
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count_rx <= count_rx + 1;
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end if;
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end if;
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end process;
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PROC_RX_RE: process
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begin
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wait for 10 us;
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rx_re <= status.rx_present;
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end process;
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PROC_DATAREG_TX: process
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begin
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wait until rising_edge(clk) and tx_we = '1';
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data_tx <= tx_din;
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end process;
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------------------------------------------------------------------------------------------
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STIMULUS: process
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begin
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wait for 3*CLK_PERIOD;
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rst <= '0';
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wait for 3*CLK_PERIOD;
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wait until rising_edge(clk);
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for i in 0 to 255 loop
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wait until rising_edge(clk);
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tx_din <= to_unsigned(i, 8);
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tx_we <= '1';
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wait until rising_edge(clk) and status.tx_full = '0';
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tx_we <= '0';
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end loop;
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wait;
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end process;
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end architecture behave;
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