jens ed3b12acda - added ise project files ...

git-svn-id: http://moon:8086/svn/vhdl/trunk@1431 cc03376c-175c-47c8-b038-4cd826a8556b

2021-03-21 12:33:59 +00:00

Common

- target run only runs simmulation without dumping anything for wave

2021-03-20 12:15:14 +00:00

lib

- run for 1500 us

2021-03-20 09:07:13 +00:00

projects

- added ise project files

2021-03-21 12:33:59 +00:00

S

Description

No description provided

23 MiB

Languages

VHDL 90.1%

Verilog 4.2%

Tcl 2.5%

SystemVerilog 0.8%

IGOR Pro 0.5%

Other 1.5%