jens
d61b3c2e0c
git-svn-id: http://moon:8086/svn/vhdl/trunk@1416 cc03376c-175c-47c8-b038-4cd826a8556b
156 lines
4.5 KiB
VHDL
156 lines
4.5 KiB
VHDL
--
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-- Interrupt test for KCPSM3
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--
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-- Ken Chapman - Xilinx Ltd - June 2003
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--
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--
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------------------------------------------------------------------------------------
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--
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-- Library declarations
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--
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-- Standard IEEE libraries
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--
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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--
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------------------------------------------------------------------------------------
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--
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--
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entity kcpsm3_int_test is
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Port ( counter : out std_logic_vector(7 downto 0);
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waveforms : out std_logic_vector(7 downto 0);
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interrupt_event : in std_logic;
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clk : in std_logic);
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end kcpsm3_int_test;
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--
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------------------------------------------------------------------------------------
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--
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-- Start of test achitecture
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--
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architecture Behavioral of kcpsm3_int_test is
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--
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------------------------------------------------------------------------------------
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--
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-- declaration of KCPSM3
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--
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component kcpsm3
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Port ( address : out std_logic_vector(9 downto 0);
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instruction : in std_logic_vector(17 downto 0);
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port_id : out std_logic_vector(7 downto 0);
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write_strobe : out std_logic;
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out_port : out std_logic_vector(7 downto 0);
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read_strobe : out std_logic;
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in_port : in std_logic_vector(7 downto 0);
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interrupt : in std_logic;
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interrupt_ack : out std_logic;
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reset : in std_logic;
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clk : in std_logic);
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end component;
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--
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-- declaration of program ROM
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--
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component int_test
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Port ( address : in std_logic_vector(9 downto 0);
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instruction : out std_logic_vector(17 downto 0);
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clk : in std_logic);
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end component;
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--
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------------------------------------------------------------------------------------
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--
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-- Signals used to connect KCPSM3 to program ROM and I/O logic
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--
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signal address : std_logic_vector(9 downto 0);
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signal instruction : std_logic_vector(17 downto 0);
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signal port_id : std_logic_vector(7 downto 0);
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signal out_port : std_logic_vector(7 downto 0);
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signal in_port : std_logic_vector(7 downto 0);
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signal write_strobe : std_logic;
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signal read_strobe : std_logic;
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signal interrupt : std_logic :='0';
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signal interrupt_ack : std_logic;
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signal reset : std_logic;
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--
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------------------------------------------------------------------------------------------------------------------------------------------------------------------------
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--
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-- Start of circuit description
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--
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begin
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-- Inserting KCPSM3 and the program memory
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processor: kcpsm3
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port map( address => address,
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instruction => instruction,
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port_id => port_id,
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write_strobe => write_strobe,
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out_port => out_port,
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read_strobe => read_strobe,
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in_port => in_port,
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interrupt => interrupt,
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interrupt_ack => interrupt_ack,
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reset => reset,
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clk => clk);
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program: int_test
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port map( address => address,
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instruction => instruction,
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clk => clk);
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-- Unused inputs on processor
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in_port <= "00000000";
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reset <= '0';
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-- Adding the output registers to the processor
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IO_registers: process(clk)
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begin
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if clk'event and clk='1' then
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-- waveform register at address 02
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if port_id(1)='1' and write_strobe='1' then
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waveforms <= out_port;
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end if;
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-- Interrupt Counter register at address 04
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if port_id(2)='1' and write_strobe='1' then
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counter <= out_port;
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end if;
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end if;
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end process IO_registers;
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-- Adding the interrupt input
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-- Note that the initial value of interrupt (low) is
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-- defined at signal declaration.
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interrupt_control: process(clk)
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begin
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if clk'event and clk='1' then
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if interrupt_ack='1' then
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interrupt <= '0';
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elsif interrupt_event='1' then
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interrupt <= '1';
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else
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interrupt <= interrupt;
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end if;
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end if;
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end process interrupt_control;
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end Behavioral;
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------------------------------------------------------------------------------------
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--
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-- END OF FILE KCPSM3_INT_TEST.VHD
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--
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------------------------------------------------------------------------------------
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