157 lines
4.0 KiB
VHDL
157 lines
4.0 KiB
VHDL
-------------------------------------------------------------------------
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-- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
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-- This file: Testbench for JCPU
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-- also writes 'opc.lst' for JASM-assembler
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--
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-- Copyright (C) 2007 J. Ahrensfeld
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--
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-- This program is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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--
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-- For questions and ideas, please contact the author at jens@jayfield.org
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--
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--------------------------------------------------------------------------
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LIBRARY ieee;
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use IEEE.STD_LOGIC_1164.ALL;
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USE ieee.numeric_std.ALL;
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use std.textio.all; -- Imports the standard textio package.
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library work;
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use work.mips_types.all;
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use work.mips_instr.all;
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ENTITY tb_eval_muldiv IS
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END tb_eval_muldiv;
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ARCHITECTURE behavior OF tb_eval_muldiv IS
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constant CLK_PERIOD : time := 10 ns;
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signal rst : std_logic := '1';
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signal clk : std_logic := '1';
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signal ce : std_logic := '0';
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signal mul_divn : std_logic := '1';
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signal op_valid : std_logic := '0';
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signal op1_in : word_t := (others => '-');
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signal op2_in : word_t := (others => '-');
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signal result : unsigned (2*word_t'length-1 downto 0);
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signal res_valid : std_logic;
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signal busy : std_logic;
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signal result_reg : unsigned (2*word_t'length-1 downto 0);
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subtype pp_t is unsigned (39 downto 0);
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signal pp0, pp1, pp2, pp3 : pp_t;
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signal signed_mul : std_logic := '1';
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signal sign1 : std_logic;
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signal sign2 : std_logic;
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signal cy : std_logic;
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BEGIN
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sign1 <= signed_mul and op1_in(op1_in'left);
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sign2 <= signed_mul and op2_in(op1_in'left);
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cy <= sign1;
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pp0 <= op1_in * op2_in(7 downto 0);
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pp1 <= op1_in * op2_in(15 downto 8);
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pp2 <= op1_in * op2_in(23 downto 16);
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pp3 <= op1_in * op2_in(31 downto 24);
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result <= ((63 downto 40 => '0') & pp0)
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+ ((63 downto 48 => '0') & pp1 & (7 downto 0 => '0'))
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+ ((63 downto 56 => '0') & pp2 & (15 downto 0 => '0'))
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+ (pp3 & (23 downto 0 => '0'));
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result_reg <= (63 downto 0 => sign1) xor (result + ((63 downto 0 => sign1) and X"0000_0000_0000_0000"));
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CLK_GEN: process
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begin
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wait for CLK_PERIOD/2;
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clk <= not clk;
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end process;
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STIMULUS: process
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begin
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wait for 3*CLK_PERIOD;
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wait until rising_edge(clk);
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rst <= '0';
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wait for 10*CLK_PERIOD;
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wait until rising_edge(clk);
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ce <= '1';
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wait for 10*CLK_PERIOD;
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op1_in <= X"FFFF_FFFA"; -- (-6)
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op2_in <= X"0000_0005"; -- (+5)
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op_valid <= '1';
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wait until rising_edge(clk);
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op_valid <= '0';
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wait for 10*CLK_PERIOD;
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op1_in <= X"0000_0006"; -- (+6)
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op2_in <= X"FFFF_FFFB"; -- (-5)
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op_valid <= '1';
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wait until rising_edge(clk);
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op_valid <= '0';
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wait for 10*CLK_PERIOD;
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op1_in <= X"1234_5678";
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op2_in <= X"8765_4321";
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op_valid <= '1';
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wait until rising_edge(clk);
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op_valid <= '0';
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wait for 10*CLK_PERIOD;
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op1_in <= X"8765_4321";
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op2_in <= X"1234_5678";
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op_valid <= '1';
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wait until rising_edge(clk);
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op_valid <= '0';
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wait for 10*CLK_PERIOD;
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op1_in <= X"1234_5678";
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op2_in <= X"1234_5678";
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op_valid <= '1';
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wait until rising_edge(clk);
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op_valid <= '0';
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wait for 10*CLK_PERIOD;
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op1_in <= X"8765_4321";
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op2_in <= X"8765_4321";
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op_valid <= '1';
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wait until rising_edge(clk);
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op_valid <= '0';
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wait for 10*CLK_PERIOD;
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op1_in <= X"789A_BCDE";
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op2_in <= X"8765_4321";
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op_valid <= '1';
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wait until rising_edge(clk);
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op_valid <= '0';
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wait for 10*CLK_PERIOD;
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op1_in <= X"8765_4321";
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op2_in <= X"789A_BCDE";
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op_valid <= '1';
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wait until rising_edge(clk);
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op_valid <= '0';
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wait;
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end process;
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END;
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