-------------------------------------------------------------------------
-- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
-- This file: Testbench for JCPU
--            also writes 'opc.lst' for JASM-assembler
--
-- Copyright (C) 2007 J. Ahrensfeld
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
--
-- For questions and ideas, please contact the author at jens@jayfield.org
--
--------------------------------------------------------------------------

LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;
use std.textio.all; --  Imports the standard textio package.

library work;
use work.mips_types.all;
use work.mips_instr.all;

ENTITY tb_eval_muldiv IS
END tb_eval_muldiv;

ARCHITECTURE behavior OF tb_eval_muldiv IS 

	constant CLK_PERIOD : time := 10 ns;
	signal rst 			: std_logic := '1';
	signal clk 			: std_logic := '1';
	signal ce  			: std_logic := '0';
	signal mul_divn		: std_logic := '1';
	signal op_valid		: std_logic := '0';
	signal op1_in		: word_t := (others => '-');
	signal op2_in		: word_t := (others => '-');
	signal result		: unsigned (2*word_t'length-1 downto 0);
	signal res_valid 	: std_logic;
	signal busy 		: std_logic;
	signal result_reg	: unsigned (2*word_t'length-1 downto 0);
	subtype pp_t is unsigned (39 downto 0);
	
	signal pp0, pp1, pp2, pp3 : pp_t;
	
	signal signed_mul	: std_logic := '1';
	signal sign1 		: std_logic;
	signal sign2 		: std_logic;
	signal cy			: std_logic;
	
BEGIN
	
	sign1	<= signed_mul and op1_in(op1_in'left);
	sign2	<= signed_mul and op2_in(op1_in'left);
	cy 		<= sign1;
	
	pp0 <= op1_in * op2_in(7 downto 0);
	pp1 <= op1_in * op2_in(15 downto 8);
	pp2 <= op1_in * op2_in(23 downto 16);
	pp3 <= op1_in * op2_in(31 downto 24);
	
	result	<= ((63 downto 40 => '0') & pp0)
			+ ((63 downto 48 => '0') & pp1 & (7 downto 0 => '0'))
			+ ((63 downto 56 => '0') & pp2 & (15 downto 0 => '0'))
			+ (pp3 & (23 downto 0 => '0'));
		
	result_reg	<= (63 downto 0 => sign1) xor (result + ((63 downto 0 => sign1) and X"0000_0000_0000_0000"));
	
CLK_GEN: process
	begin
		wait for CLK_PERIOD/2;
		clk <= not clk;
	end process;

STIMULUS: process

	begin

		wait for 3*CLK_PERIOD;
		wait until rising_edge(clk);
		rst <= '0';
		wait for 10*CLK_PERIOD;
	
		wait until rising_edge(clk);
		ce <= '1';

		wait for 10*CLK_PERIOD;
		op1_in		<= X"FFFF_FFFA"; -- (-6)
		op2_in		<= X"0000_0005"; -- (+5)
		op_valid	<= '1';
		wait until rising_edge(clk);
		op_valid	<= '0';
		
		wait for 10*CLK_PERIOD;
		op1_in		<= X"0000_0006"; -- (+6)
		op2_in		<= X"FFFF_FFFB"; -- (-5)
		op_valid	<= '1';
		wait until rising_edge(clk);
		op_valid	<= '0';
		
		wait for 10*CLK_PERIOD;
		op1_in		<= X"1234_5678";
		op2_in		<= X"8765_4321";
		op_valid	<= '1';
		wait until rising_edge(clk);
		op_valid	<= '0';
		
		wait for 10*CLK_PERIOD;
		op1_in		<= X"8765_4321";
		op2_in		<= X"1234_5678";
		op_valid	<= '1';
		wait until rising_edge(clk);
		op_valid	<= '0';

		wait for 10*CLK_PERIOD;
		op1_in		<= X"1234_5678";
		op2_in		<= X"1234_5678";
		op_valid	<= '1';
		wait until rising_edge(clk);
		op_valid	<= '0';

		wait for 10*CLK_PERIOD;
		op1_in		<= X"8765_4321";
		op2_in		<= X"8765_4321";
		op_valid	<= '1';
		wait until rising_edge(clk);
		op_valid	<= '0';

		wait for 10*CLK_PERIOD;
		op1_in		<= X"789A_BCDE";
		op2_in		<= X"8765_4321";
		op_valid	<= '1';
		wait until rising_edge(clk);
		op_valid	<= '0';

		wait for 10*CLK_PERIOD;
		op1_in		<= X"8765_4321";
		op2_in		<= X"789A_BCDE";
		op_valid	<= '1';
		wait until rising_edge(clk);
		op_valid	<= '0';

		wait; 
	
	end process;
	
END;