jens
5309734167
git-svn-id: http://moon:8086/svn/vhdl/trunk@1422 cc03376c-175c-47c8-b038-4cd826a8556b
61 lines
1.4 KiB
VHDL
61 lines
1.4 KiB
VHDL
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-- Company:
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-- Engineer:
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--
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-- Create Date: 07:53:41 10/28/05
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-- Design Name:
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-- Module Name: parity_bitser - Behavioral
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-- Project Name:
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-- Target Device:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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--------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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---- Uncomment the following library declaration if instantiating
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---- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity parity_bitser is
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Port ( rst : in std_logic;
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clk : in std_logic;
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srst : in std_logic;
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ce : in std_logic;
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d_in : in std_logic;
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parity : out std_logic);
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end parity_bitser;
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architecture Behavioral of parity_bitser is
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signal parity_i : std_logic;
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begin
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process (rst, srst, clk, ce, d_in)
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begin
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if rst='1' then
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parity_i <= '1';
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elsif clk='1' and clk'event then
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if srst='1' then
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parity_i <= '1';
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elsif ce = '1' and d_in = '1' then
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parity_i <= not parity_i;
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end if;
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end if;
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end process;
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parity <= parity_i;
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end Behavioral;
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